CC2540F128,CC2540F256
https://www.doczj.com/doc/7c8679782.html, SWRS084C–OCTOBER2010–REVISED NOVEMBER2011
2.4-GHz Bluetooth?low energy System-on-Chip
Check for Samples:CC2540F128,CC2540F256
FEATURES?TPS62730Compatible
Low Power in Active Mode
?True Single-Chip BLE Solution:CC2540Can
–RX Down to15.8mA(3V Supply) Run Both Application and BLE Protocol Stack,
Includes Peripherals to Interface With Wide–TX(-6dBm):18.6mA(3V Supply)
Range of Sensors,Etc.
?6-mm×6-mm Package?Microcontroller
?RF–High-Performance and Low-Power8051
Microcontroller Core
–Bluetooth low energy technology
Compatible–In-System-Programmable Flash,128KB or
256KB
–Excellent Link Budget(up to97dB),
Enabling Long-Range Applications Without–8-KB SRAM
External Front End
–Accurate Digital Received Signal-Strength?Peripherals
Indicator(RSSI)–12-Bit ADC with Eight Channels and –Suitable for Systems Targeting Compliance Configurable Resolution With Worldwide Radio Frequency–Integrated High-Performance Op-Amp and Regulations:ETSI EN300328and EN300Ultralow-Power Comparator
440Class2(Europe),FCC CFR47Part15
–General-Purpose Timers(One16-Bit,Two (US),and ARIB STD-T66(Japan)
8-Bit)
?Layout
–21General-Purpose I/O Pins(19×4mA,2×–Few External Components20mA)
–Reference Design Provided–32-kHz Sleep Timer With Capture
–6-mm×6-mm QFN40Package–Two Powerful USARTs With Support for ?Low Power Several Serial Protocols –Active Mode RX Down to19.6mA–Full-Speed USB Interface
–Active Mode TX(–6dBm):24mA–IR Generation Circuitry
–Power Mode1(3-μs Wake-Up):235μA–Powerful Five-Channel DMA
–Power Mode2(Sleep Timer On):0.9μA–AES Security Coprocessor
–Power Mode3(External Interrupts):0.4μA–Battery Monitor and Temperature Sensor –Wide Supply Voltage Range(2V–3.6V)–Each CC2540Contains a Unique48-bit
IEEE Address
–Full RAM and Register Retention in All
Power Modes
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SmartRF is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG,Inc.
Supported by IAR Embedded Workbench is a trademark of IAR Systems AB.
ZigBee is a registered trademark of ZigBee Alliance.
CC2540F128,CC2540F256
SWRS084C–OCTOBER2010–REVISED https://www.doczj.com/doc/7c8679782.html, SOFTWARE FEATURES APPLICATIONS
?Bluetooth v4.0Compliant Protocol Stack for? 2.4-GHz Bluetooth low energy Systems Single-Mode BLE Solution?Mobile Phone Accessories
–Complete Power-Optimized Stack,?Sports and Leisure Equipment Including Controller and Host?Consumer Electronics
–GAP–Central,Peripheral,Observer,or?Human Interface Devices(Keyboard,Mouse, Broadcaster(Including Combination Remote Control)
Roles)
?USB Dongles
–ATT/GATT–Client and Server
?Health Care and Medical
–SMP–AES-128Encryption and
Decryption CC2540WITH TPS62730
–L2CAP
?TPS62730is a2MHz Step Down Converter –Sample Applications and Profiles with Bypass Mode
–Generic Applications for GAP Central?Extends Battery Lifetime by up to20% and Peripheral Roles
?Reduced Current in TX and RX –Proximity,Accelerometer,Simple Keys,
?30nA Bypass Mode Current to Support Low and Battery GATT Services
Power Modes
–Multiple Configuration options
?RF Performance Unchanged –Single-Chip Configuration,Allowing
?Small Package Allows for Small Solution Size Application to Run on CC2540
?CC2540Controllable
–Network Processor Interface for
Applications Running on an External
Microcontroller
–BTool–Windows PC Application for
Evaluation,Development,and Test
?Development Tools
–CC2540Mini Development Kit
–SmartRF?Software
–Supported by IAR Embedded Workbench?
Software for8051
DESCRIPTION
The CC2540is a cost-effective,low-power,true system-on-chip(SoC)for Bluetooth low energy applications.It enables robust BLE master or slave nodes to be built with very low total bill-of-material costs.The CC2540 combines an excellent RF transceiver with an industry-standard enhanced8051MCU,in-system programmable flash memory,8-KB RAM,and many other powerful supporting features and peripherals.The CC2540is suitable for systems where very low power consumption is required.Very low-power sleep modes are available.Short transition times between operating modes further enable low power consumption.
The CC2540comes in two different versions:CC2540F128/F256,with128and256KB of flash memory, respectively.
Combined with the Bluetooth low energy protocol stack from Texas Instruments,the CC2540F128/F256forms the market’s most flexible and cost-effective single-mode Bluetooth low energy solution.
2Submit Documentation Feedback Copyright?2010–2011,Texas Instruments Incorporated
RESET_N
XOSC_Q2
XOSC_Q1
P2_4
P1_7
P0_7
P2_3
P1_6
P0_6
P2_2
P1_5
P0_5
P1_2
P0_2
P2_1
P1_4
P0_4
P1_1
P0_1P2_0P1_3
P0_3
P1_0
P0_0USB_N
USB_P CC2540F128,CC2540F256
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Copyright ?2010–2011,Texas Instruments Incorporated Submit Documentation Feedback 3
CC2540F128,CC2540F256
SWRS084C–OCTOBER2010–REVISED https://www.doczj.com/doc/7c8679782.html, This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
MIN MAX UNIT Supply voltage All supply pins must have the same voltage–0.3 3.9V
–0.3VDD+0.3,
Voltage on any digital pin V
≤3.9
Input RF level10dBm Storage temperature range–40125°C
All pads,according to human-body model,JEDEC STD22,method A1142kV ESD(2)
According to charged-device model,JEDEC STD22,method C101750V (1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratings
only,and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)CAUTION:ESD sensitive device.Precautions should be used when handing the device in order to prevent permanent damage. RECOMMENDED OPERATING CONDITIONS
MIN MAX UNIT Operating ambient temperature range,T A–4085°C Operating supply voltage2 3.6V ELECTRICAL CHARACTERISTICS
Measured on Texas Instruments CC2540EM reference design with T A=25°C and VDD=3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power mode1.Digital regulator on;16-MHz RCOSC and
32-MHz crystal oscillator off;32.768-kHz XOSC,POR,BOD235
and sleep timer active;RAM and register retention
Power mode2.Digital regulator off;16-MHz RCOSC and
μA
32-MHz crystal oscillator off;32.768-kHz XOSC,POR,and0.9
I core Core current consumption sleep timer active;RAM and register retention
Power mode3.Digital regulator off;no clocks;POR active;
0.4
RAM and register retention
Low MCU activity:32-MHz XOSC running.No radio or
6.7mA
peripherals.No flash access,no RAM access.
Timer1.Timer running,32-MHz XOSC used90μA
Timer2.Timer running,32-MHz XOSC used90μA Peripheral current consumption Timer3.Timer running,32-MHz XOSC used60μA I peri(Adds to core current I core for each
Timer4.Timer running,32-MHz XOSC used70μA peripheral unit activated)
Sleep timer,including32.753-kHz RCOSC0.6μA
ADC,when converting 1.2mA 4Submit Documentation Feedback Copyright?2010–2011,Texas Instruments Incorporated
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GENERAL CHARACTERISTICS
Measured on Texas Instruments CC2540EM reference design with T A=25°C and VDD=3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT WAKE-UP AND TIMING
Digital regulator on,16-MHz RCOSC and32-MHz crystal
Power mode1→Active4μs
oscillator off.Start-up of16-MHz RCOSC
Digital regulator off,16-MHz RCOSC and32-MHz crystal
Power mode2or3→Active120μs
oscillator off.Start-up of regulator and16-MHz RCOSC
Crystal ESR=16?.Initially running on16-MHz RCOSC,
410μs
with32-MHz XOSC OFF
Active→TX or RX
With32-MHz XOSC initially on160μs
RX/TX turnaround150μs RADIO PART
RF frequency range Programmable in2-MHz steps24022480MHz Data rate and modulation format1Mbps,GFSK,250kHz deviation
RF RECEIVE SECTION
Measured on Texas Instruments CC2540EM reference design with T A=25°C,VDD=3V,f c=2440MHz
1Mbps,GFSK,250-kHz deviation,Bluetooth low energy mode,and0.1%BER(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Receiver sensitivity(2)High-gain mode–93dBm Receiver sensitivity(2)Standard mode–87dBm Saturation(3)6dBm Co-channel rejection(3)–5dB Adjacent-channel rejection(3)±1MHz–5dB Alternate-channel rejection(3)±2MHz30dB Blocking(3)–30dBm Frequency error tolerance(4)Including both initial tolerance and drift–250250kHz Symbol rate error tolerance(5)–8080ppm
Conducted measurement with a50-Ωsingle-ended load.
Spurious emission.Only largest spurious
Complies with EN300328,EN300440class2,FCC CFR47,–75dBm emission stated within each band.
Part15and ARIB STD-T-66
RX mode,standard mode,no peripherals active,low MCU
19.6
activity,MCU at250kHz
Current consumption mA
RX mode,high-gain mode,no peripherals active,low MCU
22.1
activity,MCU at250kHz
(1)0.1%BER maps to30.8%PER
(2)The receiver sensitivity setting is programmable using a TI BLE stack vendor-specific API command.The default value is standard
mode.
(3)Results based on standard gain mode
(4)Difference between center frequency of the received RF signal and local oscillator frequency
(5)Difference between incoming symbol rate and the internally generated symbol rate
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CC2540F128,CC2540F256
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RF TRANSMIT SECTION
Measured on Texas Instruments CC2540EM reference design with T A=25°C,VDD=3V and f c=2440MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Delivered to a single-ended50-Ωload through a balun using
4
maximum recommended output power setting
Output power dBm
Delivered to a single-ended50-Ωload through a balun using minimum
–20
recommended output power setting
Programmable output power Delivered to a single-ended50Ωload through a balun24dB range
Conducted measurement with a50-Ωsingle-ended https://www.doczj.com/doc/7c8679782.html,plies
Spurious emissions with EN300328,EN300440class2,FCC CFR47,Part15and ARIB–41dBm
STD-T-66(1)
TX mode,–23-dBm output power,no peripherals active,low MCU
21.1
activity,MCU at250kHz
TX mode,–6-dBm output power,no peripherals active,low MCU
23.8
activity,MCU at250kHz
Current consumption mA
TX mode,0-dBm output power,no peripherals active,low MCU
27
activity,MCU at250kHz
TX mode,4-dBm output power,no peripherals active,low MCU
31.6
activity,MCU at250kHz
Differential impedance as seen from the RF port(RF_P and RF_N)
Optimum load impedance70+j30Ω
toward the antenna
(1)Designs with antenna connectors that require conducted ETSI compliance at64MHz should insert an LC resonator in front of the
antenna https://www.doczj.com/doc/7c8679782.html,e a1.6-nH inductor in parallel with a1.8-pF capacitor.Connect both from the signal trace to a good RF ground. CURRENT CONSUMPTION WITH TPS62730
Measured on Texas Instruments CC2540TPS62730EM reference design with T A=25°C,VDD=3V,and f c=2440MHZ.
1Mbps,GFSK,250kHz deviation,Bluetooth?low energy mode,1%BER(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RX mode,standard mode,no peripherals active,low MCU activity,MCU at1
15.8
MHZ
RX mode,high-gain mode,no peripherals active,low MCU activity,MCU at1
17.8
MHZ
TX mode,-23dBm output power,no peripherals active,low MCU activity,
16.5
MCU at1MHZ
Current Consumption mA TX mode,-6dBm output power,no peripherals active,low MCU activity,MCU
18.6
at1MHZ
TX mode,0dBm output power,no peripherals active,low MCU activity,MCU
21
at1MHZ
TX mode,4dBm output power,no peripherals active,low MCU activity,MCU
24.6
at1MHZ
(1)0.1%BER maps to30.8%PER
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32-MHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2540EM reference design with T A=25°C and VDD=3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Crystal frequency32MHz Crystal frequency accuracy
–4040ppm requirement(1)
ESR Equivalent series resistance660?
C0Crystal shunt capacitance17pF
C L Crystal load capacitance1016pF
Start-up time0.25ms
The crystal oscillator must be in power down for a
guard time before it is used again.This
Power-down guard time requirement is valid for all modes of operation.The3ms
need for power-down guard time can vary with
crystal type and load.
(1)Including aging and temperature dependency,as specified by[1]
32.768-kHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2540EM reference design with T A=25°C and VDD=3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Crystal frequency32.768kHz
Crystal frequency accuracy
–4040ppm requirement(1)
ESR Equivalent series resistance40130k?
C0Crystal shunt capacitance0.92pF
C L Crystal load capacitance1216pF
Start-up time0.4s (1)Including aging and temperature dependency,as specified by[1]
32-kHz RC OSCILLATOR
Measured on Texas Instruments CC2540EM reference design with Tω=25°C and VDD=3V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Calibrated frequency(1)32.753kHz Frequency accuracy after calibration±0.2%
Temperature coefficient(2)0.4%/°C Supply-voltage coefficient(3)3%/V Calibration time(4)2ms
(1)The calibrated32-kHz RC oscillator frequency is the32-MHz XTAL frequency divided by977.
(2)Frequency drift when temperature changes after calibration
(3)Frequency drift when supply voltage changes after calibration
(4)When the32-kHz RC oscillator is enabled,it is calibrated when a switch from the16-MHz RC oscillator to the32-MHz crystal oscillator
is performed while SLEEPCMD.OSC32K_CALDIS is set to0.
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CC2540F128,CC2540F256
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16-MHz RC OSCILLATOR
Measured on Texas Instruments CC2540EM reference design with T A=25°C and VDD=3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency(1)16MHz Uncalibrated frequency accuracy±18%
Calibrated frequency accuracy±0.6%
Start-up time10μs Initial calibration time(2)50μs
(1)The calibrated16-MHz RC oscillator frequency is the32-MHz XTAL frequency divided by2.
(2)When the16-MHz RC oscillator is enabled,it is calibrated when a switch from the16-MHz RC oscillator to the32-MHz crystal oscillator
is performed while SLEEPCMD.OSC_PD is set to0.
RSSI CHARACTERISTICS
Measured on Texas Instruments CC2540EM reference design with T A=25°C and VDD=3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-gain mode–99to–44
Useful RSSI range(1)dBm
Standard mode–90to–35
Absolute uncalibrated RSSI accuracy(1)High-gain mode±4dB Step size(LSB value)1dB (1)Assuming CC2540EM reference design.Other RF designs give an offset from the reported value.
FREQUENCY SYNTHESIZER CHARACTERISTICS
Measured on Texas Instruments CC2540EM reference design with T A=25°C,VDD=3V and f c=2440MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
At±1-MHz offset from carrier–109
Phase noise,unmodulated
At±3-MHz offset from carrier–112dBc/Hz carrier
At±5-MHz offset from carrier–119
ANALOG TEMPERATURE SENSOR
Measured on Texas Instruments CC2540EM reference design with T A=25°C and VDD=3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output148012-bit Temperature coefficient 4.5mv/°C Voltage coefficient1/0.1V
Measured using integrated ADC,internal band-gap voltage
reference,and maximum resolution
Initial accuracy without calibration±10°C Accuracy using1-point calibration±5°C Current consumption when enabled0.5mA
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OP-AMP CHARACTERISTICS
T A=25°C,VDD=3V,.All measurement results are obtained using the CC2540reference designs post-calibration.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Chopping Configuration,Register APCFG=0x07,OPAMPMC=0x03,OPAMPC=0x01
Output maximum voltage VDD–0.1V
Output minimum voltage0.1V
Open-loop gain108dB
Gain-bandwidth product2MHz
Slew rate 2.6V/μs
Input maximum voltage VDD V
Intput minimum voltage0mV
Input offset voltage40μV CMRR Common-mode rejection ratio90dB Supply current0.4mA
f=0.01Hz to1Hz 1.1 Input noise voltage nV/√(Hz)
f=0.1Hz to10Hz 1.7
Non-Chopping Configuration,Register APCFG=0x07,OPAMPMC=0x00,OPAMPC=0x01
Output maximum voltage VDD–0.1V
Output minimum voltage0.1V
Open-loop gain108dB
Gain-bandwidth product2MHz
Slew rate 2.6V/μs
Input maximum voltage VDD V
Intput minimum voltage0mV
Input offset voltage 3.2mV CMRR Common-mode rejection ratio90dB Supply current0.4mA
f=0.01Hz to1Hz60 Input noise voltage nV/√(Hz)
f=0.1Hz to10Hz65 COMPARATOR CHARACTERISTICS
T A=25°C,VDD=3V.All measurement results are obtained using the CC2540reference designs,post-calibration.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Common-mode maximum voltage VDD V
Common-mode minimum voltage–0.3
Input offset voltage1mV
Offset vs temperature16μV/°C
Offset vs operating voltage4mV/V
Supply current230nA
Hysteresis0.15mV Copyright?2010–2011,Texas Instruments Incorporated Submit Documentation Feedback9
CC2540F128,CC2540F256
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ADC CHARACTERISTICS
T A=25°C and VDD=3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input voltage VDD is voltage on AVDD5pin0VDD V
External reference voltage VDD is voltage on AVDD5pin0VDD V
External reference voltage differential VDD is voltage on AVDD5pin0VDD V
Input resistance,signal Simulated using4-MHz clock speed197k?
Full-scale signal(1)Peak-to-peak,defines0dBFS 2.97V
Single-ended input,7-bit setting 5.7
Single-ended input,9-bit setting7.5
Single-ended input,10-bit setting9.3
Single-ended input,12-bit setting10.3
Differential input,7-bit setting 6.5
ENOB(1)Effective number of bits bits
Differential input,9-bit setting8.3
Differential input,10-bit setting10
Differential input,12-bit setting11.5
10-bit setting,clocked by RCOSC9.7
12-bit setting,clocked by RCOSC10.9 Useful power bandwidth7-bit setting,both single and differential0–20kHz
Single ended input,12-bit setting,–6
–75.2
dBFS(1)
THD Total harmonic distortion dB
Differential input,12-bit setting,–6
–86.6
dBFS(1)
Single-ended input,12-bit setting(1)70.2
Differential input,12-bit setting(1)79.3
Single-ended input,12-bit setting,–6
Signal to nonharmonic ratio dB
78.8
dBFS(1)
Differential input,12-bit setting,–6
88.9
dBFS(1)
Differential input,12-bit setting,1-kHz
CMRR Common-mode rejection ratio>84dB
sine(0dBFS),limited by ADC resolution
Single ended input,12-bit setting,1-kHz
Crosstalk>84dB
sine(0dBFS),limited by ADC resolution
Offset Midscale–3mV
Gain error0.68%
12-bit setting,mean(1)0.05
DNL Differential nonlinearity LSB
12-bit setting,maximum(1)0.9
12-bit setting,mean(1) 4.6
12-bit setting,maximum(1)13.3
INL Integral nonlinearity LSB
12-bit setting,mean,clocked by RCOSC10
12-bit setting,max,clocked by RCOSC29
Single ended input,7-bit setting(1)35.4
Single ended input,9-bit setting(1)46.8
Single ended input,10-bit setting(1)57.5
Single ended input,12-bit setting(1)66.6
SINAD
Signal-to-noise-and-distortion dB (–THD+N)Differential input,7-bit setting(1)40.7
Differential input,9-bit setting(1)51.6
Differential input,10-bit setting(1)61.8
Differential input,12-bit setting(1)70.8
(1)Measured with300-Hz sine-wave input and VDD as reference.
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RESET
CC2540F128,CC2540F256
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ADC CHARACTERISTICS(continued)
T A=25°C and VDD=3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
7-bit setting20
9-bit setting36 Conversion timeμs
10-bit setting68
12-bit setting132 Power consumption 1.2mA
Internal reference VDD coefficient4mV/V
Internal reference temperature coefficient0.4mV/10°C
Internal reference voltage 1.15V CONTROL INPUT AC CHARACTERISTICS
T A=–40°C to85°C,VDD=2V to3.6V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
The undivided system clock is32MHz when crystal oscillator is used.
System clock,f SYSCLK
The undivided system clock is16MHz when calibrated16-MHz RC1632MHz
t SYSCLK=1/f SYSCLK oscillator is used.
See item1,Figure1.This is the shortest pulse that is recognized as
a complete reset pin request.Note that shorter pulses may be
RESET_N low duration1μs recognized but do not lead to complete reset of all modules within the
chip.
See item2,Figure1.This is the shortest pulse that is recognized as
Interrupt pulse duration20ns an interrupt request.
Figure1.Control Input AC Characteristics
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SCK
SSN
MOSI
MISO
T0478-01CC2540F128,CC2540F256
SWRS084C –OCTOBER 2010–REVISED NOVEMBER https://www.doczj.com/doc/7c8679782.html,
SPI AC CHARACTERISTICS
T A =–40°C to 85°C,VDD =2V to 3.6V
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT Master,RX and TX 250t 1SCK period
ns
Slave,RX and TX 250SCK duty cycle
Master 50%Master 63t 2
SSN low to SCK ns Slave 63Master 63t 3
SCK to SSN high ns Slave 63t 4
MOSI early out Master,load =10pF 7ns t 5
MOSI late out Master,load =10pF 10ns t 6
MISO setup Master 90ns t 7
MISO hold Master 10ns SCK duty cycle Slave 50%ns t 10
MOSI setup Slave 35ns t 11
MOSI hold Slave 10ns t 9MISO late out Slave,load =10pF
95ns Master,TX only
8Master,RX and TX
4Operating frequency MHz Slave,RX only
8Slave,RX and TX 4Figure 2.SPI Master AC Characteristics
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T0479-01SCK
SSN
MOSI MISO
CC2540F128,CC2540F256
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Figure 3.SPI Slave AC Characteristics
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DEBUG _CLK
P2_2
T0436-01
RESET _N
DEBUG _CLK P2_2
T0437-01
CC2540F128,CC2540F256
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DEBUG INTERFACE AC CHARACTERISTICS
T A =–40°C to 85°C,VDD =2V to 3.6V
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT f clk_dbg
Debug clock frequency (see Figure 4)12MHz t 1
Allowed high pulse on clock (see Figure 4)35ns t 2
Allowed low pulse on clock (see Figure 4)35ns EXT_RESET_N low to first falling edge on debug t 3
167ns clock (see Figure 6)Falling edge on clock to EXT_RESET_N high (see t 4
83ns Figure 6)EXT_RESET_N high to first debug command (see t 5
83ns Figure 6)t 6
Debug data setup (see Figure 5)2ns t 7
Debug data hold (see Figure 5)4ns t 8Clock-to-data delay (see Figure 5)Load =10pF
30ns
Figure 4.Debug Clock –Basic Timing
Figure 5.Debug Enable Timing
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DEBUG _CLK
P2_2
DEBUG _DATA
DEBUG _DATA
T0438-02
CC2540F128,CC2540F256
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Figure 6.Data Setup and Hold Timing
TIMER INPUTS AC CHARACTERISTICS
T A =–40°C to 85°C,VDD =2V to 3.6V
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT Synchronizers determine the shortest input pulse that can be Input capture pulse duration recognized.The synchronizers operate at the current system clock rate
1.5t SYSCLK
(16MHz or 32MHz).DC CHARACTERISTICS
T A =25°C,VDD =3V
PARAMETER
TEST CONDITIONS MIN TYP MAX UNIT Logic-0input voltage
0.5V Logic-1input voltage
2.5V Logic-0input current
Input equals 0V –5050nA Logic-1input current
Input equals VDD –5050nA I/O-pin pullup and pulldown resistors
20k ?Logic-0output voltage,4-mA pins
Output load 4mA 0.5V Logic-1output voltage,4-mA pins Output load 4mA 2.4V
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CC2540
RHA Package
(Top View)
P 0_1
R E S E T _N P 2_3 / X O S C 32K _Q 2
A V D D 6DVDD_USB
R_BIAS P 0_2P 0_0
AVDD4P 0_3AVDD1P 0_4AVDD2P 0_5RF_N P 0_6RF_P P 0_7AVDD3XOSC_Q1P 1_0XOSC_Q2AVDD5P 2_2P 2_4 / X O S C 32K _Q 1
USB_P
P 2_1USB_N
P 2_0DGND_USB
P 1_7P1_5
P 1_6P1_4
D V D D 1P1_3
P1_1
D C O U P L P1_2
DVDD2P0076-05
CC2540F128,CC2540F256
SWRS084C –OCTOBER 2010–REVISED NOVEMBER https://www.doczj.com/doc/7c8679782.html,
DEVICE INFORMATION
PIN DESCRIPTIONS
The CC2540pinout is shown in Figure 7and a short description of the pins follows.
NOTE:The exposed ground pad must be connected to a solid ground plane,as this is the ground connection for the chip.
Figure 7.Pinout Top View
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PIN DESCRIPTIONS
PIN NAME PIN PIN TYPE DESCRIPTION
AVDD128Power(analog)2-V–3.6-V analog power-supply connection
AVDD227Power(analog)2-V–3.6-V analog power-supply connection
AVDD324Power(analog)2-V–3.6-V analog power-supply connection
AVDD429Power(analog)2-V–3.6-V analog power-supply connection
AVDD521Power(analog)2-V–3.6-V analog power-supply connection
AVDD631Power(analog)2-V–3.6-V analog power-supply connection
DCOUPL40Power(digital) 1.8-V digital power-supply decoupling.Do not use for supplying external circuits.
DGND_USB1Ground pin Connect to GND
DVDD_USB4Power(digital)2-V–3.6-V digital power-supply connection
DVDD139Power(digital)2-V–3.6-V digital power-supply connection
DVDD210Power(digital)2-V–3.6-V digital power-supply connection
GND—Ground The ground pad must be connected to a solid ground plane.
P0_019Digital I/O Port0.0
P0_118Digital I/O Port0.1
P0_217Digital I/O Port0.2
P0_316Digital I/O Port0.3
P0_415Digital I/O Port0.4
P0_514Digital I/O Port0.5
P0_613Digital I/O Port0.6
P0_712Digital I/O Port0.7
P1_011Digital I/O Port1.0–20-mA drive capability
P1_19Digital I/O Port1.1–20-mA drive capability
P1_28Digital I/O Port1.2
P1_37Digital I/O Port1.3
P1_46Digital I/O Port1.4
P1_55Digital I/O Port1.5
P1_638Digital I/O Port1.6
P1_737Digital I/O Port1.7
P2_036Digital I/O Port2.0
P2_135Digital I/O Port2.1
P2_234Digital I/O Port2.2
P2_3/33Digital I/O,Port2.3/32.768kHz XOSC
XOSC32K_Q2Analog I/O
P2_4/32Digital I/O,Port2.4/32.768kHz XOSC
XOSC32K_Q1Analog I/O
RBIAS30Analog I/O External precision bias resistor for reference current
RESET_N20Digital input Reset,active-low
RF_N26RF I/O Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_P25RF I/O Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
USB_N3Digital I/O USB N
USB_P2Digital I/O USB P
XOSC_Q122Analog I/O32-MHz crystal oscillator pin1or external-clock input
XOSC_Q223Analog I/O32-MHz crystal oscillator pin2
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RESET_N
XOSC_Q2
XOSC_Q1
P2_4
P1_7
P0_7
P2_3
P1_6
P0_6
P2_2
P1_5
P0_5
P1_2
P0_2
P2_1
P1_4
P0_4
P1_1
P0_1P2_0P1_3
P0_3
P1_0
P0_0USB_N
USB_P CC2540F128,CC2540F256
SWRS084C –OCTOBER 2010–REVISED NOVEMBER https://www.doczj.com/doc/7c8679782.html,
BLOCK DIAGRAM
A block diagram of the CC2540is shown in Figure 8.The modules can be roughly divided into one of three
categories:CPU-related modules;modules related to power,test,and clock distribution;and radio-related
modules.In the following subsections,a short description of each module is given.
Figure https://www.doczj.com/doc/7c8679782.html,2540Block Diagram
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CPU and Memory
The8051CPU core is a single-cycle8051-compatible core.It has three different memory access busses(SFR, DATA,and CODE/XDATA),a debug interface,and an18-input extended interrupt unit.
The memory arbiter is at the heart of the system,as it connects the CPU and DMA controller with the physical memories and all peripherals through the SFR bus.The memory arbiter has four memory-access points,access of which can map to one of three physical memories:an SRAM,flash memory,and XREG/SFR registers.It is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same physical memory.
The SFR bus is drawn conceptually in Figure8as a common bus that connects all hardware peripherals to the memory arbiter.The SFR bus in the block diagram also provides access to the radio registers in the radio register bank,even though these are indeed mapped into XDATA memory space.
The8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces.The SRAM is an ultralow-power SRAM that retains its contents even when the digital part is powered off(power modes2and 3).
The128/256KB flash block provides in-circuit programmable non-volatile program memory for the device,and maps into the CODE and XDATA memory spaces.
Peripherals
Writing to the flash block is performed through a flash controller that allows page-wise erasure and4-bytewise programming.See User Guide for details on the flash controller.
A versatile five-channel DMA controller is available in the system,accesses memory using the XDATA memory space,and thus has access to all physical memories.Each channel(trigger,priority,transfer mode,addressing mode,source and destination pointers,and transfer count)is configured with DMA descriptors that can be located anywhere in memory.Many of the hardware peripherals(AES core,flash controller,USARTs,timers, ADC interface,etc.)can be used with the DMA controller for efficient operation by performing data transfers between a single SFR or XREG address and flash/SRAM.
Each CC2540contains a unique48-bit IEEE address that can be used as the public device address for a Bluetooth device.Designers are free to use this address,or provide their own,as described in the Bluetooth specfication.
The interrupt controller services a total of18interrupt sources,divided into six interrupt groups,each of which is associated with one of four interrupt priorities.I/O and sleep timer interrupt requests are serviced even if the device is in a sleep mode(power modes1and2)by bringing the CC2540back to the active mode.
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging. Through this debug interface,it is possible to erase or program the entire flash memory,control which oscillators are enabled,stop and start execution of the user program,execute instructions on the8051core,set code breakpoints,and single-step through instructions in the https://www.doczj.com/doc/7c8679782.html,ing these techniques,it is possible to perform in-circuit debugging and external flash programming elegantly.
The I/O controller is responsible for all general-purpose I/O pins.The CPU can configure whether peripheral modules control certain pins or whether they are under software control,and if so,whether each pin is configured as an input or output and if a pullup or pulldown resistor in the pad is connected.Each peripheral that connects to the I/O pins can choose between two different I/O pin locations to ensure flexibility in various applications.
The sleep timer is an ultralow-power timer that can either use an external32.768-kHz crystal oscillator or an internal32.753-kHz RC oscillator.The sleep timer runs continuously in all operating modes except power mode 3.Typical applications of this timer are as a real-time counter or as a wake-up timer to get out of power modes1 or2.
A built-in watchdog timer allows the CC2540to reset itself if the firmware hangs.When enabled by software, the watchdog timer must be cleared periodically;otherwise,it resets the device when it times out.
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CC2540F128,CC2540F256
SWRS084C–OCTOBER2010–REVISED https://www.doczj.com/doc/7c8679782.html, Timer1is a16-bit timer with timer/counter/PWM functionality.It has a programmable prescaler,a16-bit period value,and five individually programmable counter/capture channels,each with a16-bit compare value.Each of the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals.It can also be configured in IR generation mode,where it counts timer3periods and the output is ANDed with the output of timer3to generate modulated consumer IR signals with minimal CPU interaction.
Timer2is a40-bit timer used by the Bluetooth low energy stack.It has a16-bit counter with a configurable timer period and a24-bit overflow counter that can be used to keep track of the number of periods that have transpired.A40-bit capture register is also used to record the exact time at which a start-of-frame delimiter is received/transmitted or the exact time at which transmission ends.There are two16-bit timer-compare registers and two24-bit overflow-compare registers that can be used to give exact timing for start of RX or TX to the radio or general interrupts.
Timer3and timer4are8-bit timers with timer/counter/PWM functionality.They have a programmable prescaler, an8-bit period value,and one programmable counter channel with an8-bit compare value.Each of the counter channels can be used as PWM output.
USART0and USART1are each configurable as either an SPI master/slave or a UART.They provide double buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex applications.Each USART has its own high-precision baud-rate generator,thus leaving the ordinary timers free for other uses.When configured as SPI slaves,the USARTs sample the input signal using SCK directly instead of using some oversampling scheme,and are thus well-suited for high data rates.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with 128-bit keys.The AES core also supports ECB,CBC,CFB,OFB,CTR,and CBC-MAC,as well as hardware support for CCM.
The ADC supports7to12bits of resolution with a corresponding range of bandwidths from30-kHz to4-kHz, respectively.DC and audio conversions with up to eight input channels(I/O controller pins)are possible.The inputs can be selected as single-ended or differential.The reference voltage can be internal,AVDD,or a single-ended or differential external signal.The ADC also has a temperature-sensor input channel.The ADC can automate the process of periodic sampling or conversion over a sequence of channels.
The operational amplifier is intended to provide front-end buffering and gain for the ADC.Both inputs as well as the output are available on pins,so the feedback network is fully customizable.A chopper-stabilized mode is available for applications that need good accuracy with high gain.
The ultralow-power analog comparator enables applications to wake up from PM2or PM3based on an analog signal.Both inputs are brought out to pins;the reference voltage must be provided externally.The comparator output is connected to the I/O controller interrupt detector and can be treated by the MCU as a regular I/O pin interrupt.
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