JUNE 2005
Functional Block Diagram
HIGH-SPEED 2.5V
256/128K x 72
SYNCHRONOUS
DU AL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
ADVANCED IDT70T3719/99M
5687drw 01
ZZ R
(2)
Features:
◆True Dual-Port memory cells which allow simultaneous access of the same memory location ◆
High-speed data access
–Commercial: 3.6ns (166MHz)/
4.2ns (133MHz)(max.)
–Industrial: 4.2ns (133MHz) (max.)
◆Selectable Pipelined or Flow-Through output mode ◆Counter enable and repeat features
◆
Dual chip enables allow for depth expansion without additional logic
◆Interrupt and Collision Detection Flags ◆
Full synchronous operation on both ports
–6ns cycle time, 166MHz operation (23.9Gbps bandwidth)–Fast 3.6ns clock to data out
–Self-timed write allows fast cycle time
1.Address A 17 is a NC for the IDT70T3799.
2.The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FT x and OPTx NOTES:
– 1.7ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 166MHz
–Data input, address, byte enable and control registers ◆
Separate byte controls for multiplexed bus and bus matching compatibility
◆Dual Cycle Deselect (DCD) for Pipelined Output Mode ◆ 2.5V (±100mV) power supply for core
◆
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port
◆
Industrial temperature range (-40°C to +85°C) is available at 133MHz
◆Available in a 324-pin Green Ball Grid Array (BGA)◆
Includes JTAG Functionality
Description:
The IDT70T3719/99M is a high-speed 256K/128K x 72 bit synchro-nous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to a llow s imultaneous a ccess o f a ny a ddress f rom b oth p orts. R egisters o n control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70T3719/99M has been optimized for applications having unidirec-tional o r b idirectional d ata f low i n b ursts. A n a utomatic p ower d own f eature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode.
The 70T3719/99M can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (V DD) is at 2.5V.
Pin Configuration (2,3,4,5)
70T3719/99M
BBG-324(6)
324-Pin BGA
Top View(7)
50/72/60123456789011121314151617181
A O/I R93O/I R83O/I R73O/I R63L O C L A L51A L21A L8E
B L7E B L2E
C L1S
D A L A L6A L1O/I R23O/I R33O/I R43O/I R53A
B O/I L93O/I L83O/I L73O/I L63O D T A L71)1(A L31A L01E B L6E B L5E B L1E O L T A E P E R L A L0O/I L23O/I L33O/I L43O/I L53B
C O/I R04O/I R14O/I R24O/I R34T N I L A L61A L11A L7E B L0E C L0/R W L N E T N C L A L4A L3O/I R13O/I R03O/I R92O/I R82C
D O/I L04O/I L14O/I L24O/I L34I D T C N A L41A L9
E B L4E B L3K L C L A L5A L2Z Z L O/I L13O/I L03O/I L92O/I L82D
E O/I R74O/I R64O/I R54O/I R44/L P T
F L V D D V L Q D D V R Q D D V R Q D D V L Q D D V L Q D D V R Q D D V R Q D D T P O L O/I R42O/I R52O/I R62O/I R72E
F O/I L74O/I L64O/I L54O/I L44V D D V D D V L Q D D V s s V s s V s s V D D V D D V D D V D D O/I L42O/I L52O/I L62O/I L72F
G O/I R84O/I R94O/I R05O/I R15V R Q D D V R Q D D V s s V s s V s s V s s V s s V s s V R Q D D V R Q D D O/I R32O/I R22O/I R12O/I R02G
H O/I L84O/I L94O/I L05O/I L15V L Q D D V L Q D D V s s V s s V s s V s s V s s V s s V L Q D D V L Q D D O/I L32O/I L22O/I L12O/I L02H
J O/I R55O/I R45O/I R35O/I R25V R Q D D V s s V s s V s s V s s V s s V s s V s s V s s V R Q D D O/I R61O/I R71O/I R81O/I R91J K O/I L55O/I L45O/I L35O/I L25V R Q D D V s s V s s V s s V s s V s s V s s V s s V s s V R Q D D O/I L61O/I L71O/I L81O/I L91K L O/I R65O/I R75O/I R85O/I R95V L Q D D V s s V s s V s s V s s V s s V s s V s s V s s V L Q D D O/I R51O/I R41O/I R31O/I R21L M O/I L65O/I L75O/I L85O/I L95V L Q D D V D D V s s V s s V s s V s s V s s V s s V L Q D D V L Q D D O/I L51O/I L41O/I L31O/I L21M N O/I R36O/I R26O/I R16O/I R06V R Q D D V R Q D D V L Q D D V L Q D D V s s V s s V D D V R Q D D V R Q D D V R Q D D O/I R8O/I R9O/I R01O/I R11N P O/I L36O/I L26O/I L16O/I L06Z Z R S M T V D D V D D V D D V L Q D D V L Q D D V D D V D D T P O R O/I L8O/I L9O/I L01O/I L11P R O/I R46O/I R56O/I R66O/I R76L O C R A R71)1(A R21A R9E B R4E C R0E O R A R6A R2A R1O/I R7O/I R6O/I R5O/I R4R T O/I L46O/I L56O/I L66O/I L76/L P T F R A R61A R31A R7E B R7E B R3E C R1S D A R A R4A R0O/I L7O/I L6O/I L5O/I L4T U O/I R17O/I R07O/I R96O/I R86K C T T N I R A R41A R01E B R2E B R6E B R1/R W R T A E P E R R A R3O/I R0O/I R1O/I R2O/I R3U V O/I L17O/I L07O/I L96O/I L86T S R T C N A R51A R11A R8E B R5E B R0K L C R N E T N C R A R5O/I L0O/I L1O/I L2O/I L3V 123456789011121314151617181
10l b t7865 NOTES:
1.Pin is a NC for IDT70T3799.
2.All V DD pins must be connected to 2.5V power supply.
3.All V DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DD (2.5V), and 2.5V if OPT pin for that port is
set to V SS (0V).
4.All V SS pins must be connected to ground supply.
5.Package body is approximately 19mm x 19mm x 1.4mm, with 1.76mm ball-pitch.
6.This package code is used to reference the package diagram.
7.This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port Right Port Names
CE0L, CE1L CE0R, CE1R Chip Enables (Input)(6)
R/W L R/W R Read/Write Enable (Input)
OE L OE R Output Enable (Input)
A0L - A17L(5)A0R - A17R(5)Address (Input)
I/O0L - I/O71L I/O0R - I/O71R Data Input/Output
CLK L CLK R Clock (Input)
PL/FT L PL/FT R Pipeline/Flow-Through (Input)
ADS L ADS R Address Strobe Enable (Input) CNTEN L CNTEN R Counter Enable (Input)
REPEAT L REPEAT R Counter Repeat(3)
BE0L - BE7L BE0R - BE7R Byte Enables (9-bit bytes) (Input)(6) V DDQL V DDQR Power (I/O Bus) (3.3V or 2.5V)(1) (Input) OPT L OPT R Option for selecting V DDQX(1,2) (Input)
ZZ L ZZ R Sleep Mode pin(4) (Input)
V DD Power (2.5V)(1) (Input)
V SS Ground (0V) (Input)
TDI T est Data Input
TDO T est Data Output
TCK T est Logic Clock (10MHz) (Input)
TMS T est Mode Select (Input)
TRST Reset (Initialize T AP Controller) (Input) INT L INT R Interrupt Flag (Output)
COL L COL R Collision Alert (Output)
5687 tbl 02NOTES:
1.V DD, OPT X, and V DDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2.OPT X selects the operating voltage levels for the I/Os and controls on that port.
If OPT X is set to V DD (2.5V), then that port's I/Os and controls will operate at 3.3V levels and V DDQX must be supplied at 3.3V. If OPT X is set to V SS (0V), then that port's I/Os and address controls will operate at 2.5V levels and V DDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V.
3.When REPEAT X is asserted, the counter will reset to the last valid address loaded
via ADS X.
4.The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FT x and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundry scan not be operated during sleep mode.
5.Address A17x is a NC for the IDT70T3799M.
6.Chip Enables and Byte Enables are double buffered when PL/FT = V IH, i.e., the
signals take two cycles to deselect.
NOTES:
1."H" = V IH, "L" = V IL, "X" = Don't Care.
2.ADS , CNTEN , REPEAT = Don't Care. See Truth Table II.
3.OE and ZZ are asynchronous input signals.
4.It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5.For the examples shown here, BE n may correspond to any of the eight byte enable signals.
Truth Table I—Read/Write and Enable Control (1,2,3,4,5)
OE CLK
CE 0
CE 1Byte Enables
R/W ZZ I/O Operation (6)MODE
X ?H X All BE = X X L All Bytes= High-Z Deselected: Power Down X ?X L All BE = X X L All Bytes = High-Z Deselected: Power Down X ?L H All BE = H
X L All Bytes = High-Z
All Bytes Deselected
X ?L H BE n = L, All other BE = H L L Byte n = D IN , All other Bytes = High-Z Write to Byte X Only X ?L H BE 4-7 = L, BE 0-3 = H L L Byte 4-7 = D IN , Byte 0-3 = High-Z Write to Lower Bytes Only X ?L H BE 4-7 = H, BE 0-3 = L L L Byte 4-7 = High-Z, Byte 0-3 = D IN Write to Upper Bytes Only X ?L H BE 0-7 = L
L L Byte 0-7 = D IN
Write to All Bytes
L ?L H BE n = L, All other BE = H H L Byte n = D OUT , All other Bytes = High-Z Read Byte X Only L ?L H BE 4-7 = L, BE 0-3 = H H L Byte 4-7 = D OUT , Byte 0-3 = High-Z Read Lower Bytes Only L ?L H BE 4-7 = H, BE 0-3 = L H L Byte 4-7 = High-Z, Byte 0-3 = D OUT Read Upper Bytes Only L ?L H All BE = L H L All Bytes = D OUT Read All Bytes H X X X All BE = X X L All Bytes = High-Z Outputs Disabled X
X
X
X
All BE = X
X
H
All Bytes = High-Z
Sleep Mode
5687 tbl 03
Truth Table II—Address Counter Control (1,2)
NOTES:
1."H" = V IH, "L" = V IL, "X" = Don't Care.
2.Read and write operations are controlled by the appropriate setting of R/W , CE 0, CE 1, BE n and OE .
3.Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4.ADS and REPEAT are independent of all other memory control signals including CE 0, CE 1 and BE n.
5.The address counter advances if CNTEN = V IL on the rising edge of CLK, regardless of all other memory control signals including CE 0, CE 1, BE n.
6.When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS . This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
Address Previous Internal Address
Internal Address Used CLK ADS (4)
CNTEN REPEAT (4,6)
I/O (3)MODE
An X An ?L X H D I/O (n)
External Address Used
X An An + 1?H L (5)H D I/O (n+1)Counter Enabled-Internal Address generation
X An + 1An + 1?H H H D I/O (n+1)Enabled Address Blocked-Counter disabled (An + 1 reused)X
X
An
?
X
X
L
D I/O (n)
Counter Set to last valid ADS load
5687 tbl 04
Recommended Operating
(1)
NOTES:
1.This is the parameter TA. This is the "instant on" case temperature.
5687 tbl 05
Recommended DC Operating Conditions with V DDQ at 3.3V
NOTES:
1.V IL (min.) = -1.0V for pulse width less than t CYC /2, or 5ns, whichever is less.
2.V IH (max.) = V DDQ + 1.0V for pulse width less than t CYC /2 or 5ns, whichever is less.
3.To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to V DD (2.5V), and V DDQX for that port must be supplied as indicated above.
Recommended DC Operating Conditions with V DDQ at 2.5V
NOTES:
1.V IL (min.) = -1.0V for pulse width less than t CYC /2 or 5ns, whichever is less.
2.V IH (max.) = V DDQ + 1.0V for pulse width less than t CYC /2 or 5ns, whichever is less.
3.To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT
pin for that port must be set to V ss (0V), and V DDQX for that port must be supplied as indicated above.
Symbol Parameter Min.Typ.Max.Unit V DD Core Supply Voltage 2.4 2.5 2.6V V DDQ I/O Supply Voltage (3) 2.4 2.5 2.6V V SS Ground
00
V V IH
Input High Volltage (Address, Control &Data I/O Inputs)(3) 1.7
____
V DDQ + 100mV (2)
V
V IH Input High Voltage _JT AG
1.7____
V DD + 100mV (2)V V IH Input High Voltage -ZZ, OPT , PIPE/FT V DD - 0.2V ____
V DD + 100mV (2)
V V IL Input Low Voltage -0.3(1)____
0.7V V IL
Input Low Voltage -ZZ, OPT , PIPE/FT
-0.3(1)
____
0.2
V
5687 tbl 06a
Symbol Parameter
Min.Typ.Max.Unit V DD Core Supply Voltage 2.4 2.5 2.6V V DDQ I/O Supply Voltage (3) 3.15 3.3 3.45V V SS Ground
00
V V IH
Input High Voltage (Address, Control &Data I/O Inputs)(3) 2.0
____
V DDQ + 150mV (2)
V
V IH Input High Voltage _JT AG
1.7____
V DD + 100mV (2)V V IH Input High Voltage -ZZ, OPT , PIPE/FT V DD - 0.2V ____
V DD + 100mV (2)
V V IL Input Low Voltage -0.3(1)____
0.8V V IL
Input Low Voltage -ZZ, OPT , PIPE/FT
-0.3(1)
____
0.2
V
5687 tbl 06b
Absolute Maximum Ratings (1)
Symbol Rating
Commercial & Industrial Unit V TERM (V DD )V DD T erminal Voltage with Respect to GND -0.5 to 3.6V V TERM (2)(V DDQ )
V DDQ Terminal Voltage with Respect to GND -0.3 to V DDQ + 0.3V V TERM (2)
(INPUTS and I/O's)Input and I/O T erminal
Voltage with Respect to GND -0.3 to V DDQ + 0.3
V
T BIAS (3)Temperature Under Bias -55 to +125o C T STG Storage Temperature -65 to +150o C T JN
Junction T emperature
+150o
C
I OUT (For V DDQ = 3.3V)DC Output Current 50mA I OUT (For V DDQ = 2.5V)DC Output Current
40
mA
5687 tbl 07
NOTES:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed V DDQ during power supply ramp up.3.Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
NOTES:
1.These parameters are determined by device characterization, but are not production tested.
2.C OUT also references C I/O .
Capacitance (1)
(T A = +25°C, F = 1.0MH Z )
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (V DD = 2.5V ± 100mV)
Symbol Parameter
Test Conditions
70T3719/99M
Unit Min.
Max.|I LI |Input Leakage Current (1)
V DDQ = Max., V IN = 0V to V DDQ ___10μA |I LI |JT AG & ZZ Input Leakage Current (1,2)V DD = Max., V IN = 0V to V DD
___±30μA |I LO |Output Leakage Current (1,3)CE 0 = V IH or CE 1 = V IL , V OUT = 0V to V DDQ ___10μA V OL (3.3V)Output Low Voltage (1)I OL = +4mA, V DDQ = Min.___
0.4
V V OH (3.3V)Output High Voltage (1)I OH = -4mA, V DDQ = Min. 2.4
___
V V OL (2.5V)Output Low Voltage (1)I OL = +2mA, V DDQ = Min.___
0.4
V V OH (2.5V)
Output High Voltage (1)
I OH = -2mA, V DDQ = Min.
2.0
___
V
5687 tbl 09
NOTES:
1.V DDQ is selectable (3.3V/
2.5V) via OPT pins. Refer to p.5 for details.2.Applicable only for TMS, TDI and TRST inputs.
3.Outputs tested in tri-state mode.
Symbol Parameter Conditions (2)Max.Unit C IN Input Capacitance V IN = 0V 15pF C OUT (2)
Output Capacitance
V OUT = 0V
10.5
pF
5687 tbl 08
DC Electrical Characteristics Over the Operating
(3)
1.At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t CYC, using "AC TEST CONDITIONS".
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3.Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4.V DD = 2.5V, T A = 25°C for Typ, and are not production tested. I DD DC(f=0)= 30mA (Typ).
5.CE X = V IL means CE0X = V IL and CE1X = V IH
CE X = V IH means CE0X = V IH or CE1X = V IL
CE X < 0.2V means CE0X < 0.2V and CE1X > V DD - 0.2V
CE X > V DD - 0.2V means CE0X > V DD - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6.I SB1, I SB2 and I SB4 will all reach full standby levels (I SB3) on the appropriate port(s) if ZZ L and/or ZZ R = V IH.
AC Test Conditions (V DDQ - 3.3V/2.5V)
Figure 1. AC Output Test load.
Input Pulse Levels (Address & Controls)Input Pulse Levels (I/Os)Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load
GND to 3.0V/GND to 2.4V GND to 3.0V/GND to 2.4V
2ns 1.5V/1.25V
1.5V/1.25V Figure 1
5687 tbl 11
1.5V/1.25
5687drw 03
DATA OUT
Capacitance (pF)from AC Test Load
5687drw 04
?tCD
(Typical,ns)
AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) (2,3) (V DD = 2.5V ± 100mV, T A = 0°C to +70°C)
NOTES:
1.The Pipelined output parameters (t CYC2, t CD2) apply to either or both left and right ports when FT /PIPE X = V DD (
2.5V). Flow-through parameters (t CYC1, t CD1)apply when FT /PIPE = V ss (0V) for that port.
2.All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE ), FT /PIPE and OPT. FT /PIPE and OPT should be treated as DC signals, i.e. steady state during operation.
3.These values are valid for either level of V DDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.
4.Guaranteed by design (not production tested).
70T3719/99M
S166Com'l Only
70T3719/99M
S133Com'l & Ind Symbol Parameter
Min.Max.
Min.Max.
Unit t CYC1Clock Cycle Time (Flow-Through)(1)20____25____ns t CYC2Clock Cycle Time (Pipelined)(1)6____7.5____ns t CH1Clock High Time (Flow-Through)(1)8____10____ns t CL1Clock Low Time (Flow-Through)(1)8____10____ns t CH2Clock High Time (Pipelined)(2) 2.4____3____ns t CL2Clock Low Time (Pipelined)(1) 2.4____3____ns t SA Address Setup Time 1.7____ 1.8____ns t HA Address Hold Time 0.5____0.5____ns t SC Chip Enable Setup Time 1.7____ 1.8____ns t HC Chip Enable Hold Time 0.5____0.5____ns t SB Byte Enable Setup Time 1.7____ 1.8____ns t HB Byte Enable Hold Time 0.5____0.5____ns t SW R/W Setup Time 1.7____ 1.8____ns t HW R/W Hold Time 0.5____0.5____ns t SD Input Data Setup Time 1.7____ 1.8____ns t HD Input Data Hold Time 0.5____0.5____ns t SAD ADS Setup Time 1.7____ 1.8____ns t HAD ADS Hold Time 0.5____0.5____ns t SCN CNTEN Setup Time 1.7____ 1.8____ns t HCN CNTEN Hold Time 0.5____0.5____ns t SRPT REPEAT Setup Time 1.7____ 1.8____ns t HRPT REPEAT Hold Time 0.5
____
0.5
____
ns t OE Output Enable to Data Valid ____
4.4
____
4.6
ns t OLZ (4)Output Enable to Output Low-Z 1____
1____
ns t OHZ (4)Output Enable to Output High-Z 1
3.61
4.2ns t CD1Clock to Data Valid (Flow-Through)(1)____12____15ns t CD2Clock to Data Valid (Pipelined)(1)____
3.6
____
4.2
ns t DC Data Output Hold After Clock High 1____
1____
ns t CKHZ (4)Clock High to Output High-Z 1 3.6
1 4.2
ns t CKLZ (4)Clock High to Output Low-Z 1
____
1
____
ns t INS Interrupt Flag Set Time ____7____7ns t INR Interrupt Flag Reset Time ____7____7ns t COLS Collision Flag Set Time ____ 3.6____ 4.2ns t COLR Collision Flag Reset Time ____
3.6
____
4.2
ns t ZZSC Sleep Mode Set Cycles 2____2____cycles t ZZRC
Sleep Mode Recovery Cycles
3
____
3
____
cycles
Port-to-Port Delay t CO Clock-to-Clock Offset
5
____
6
____
ns
t OFS
Clock-to-Clock Offset for Collision Detection
Please refer to collision Detection Timing T able on Page 19.
5687 tbl 12
R/W
ADDRESS
CE 0
CLK CE 1
BE n
DATA OUT OE
5687drw 05
Timing Waveform of Read Cycle for Pipelined Operation (FT 'X' IH (1,2)
NOTES:
1.OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2.ADS = V IL , CNTEN and REPEAT = V IH .
3.The output is disabled (High-Impedance state) by CE 0 = V IH , CE 1 = V IL , BE n = V IH following the next rising edge of the clock. Refer to
Truth Table 1.
4.Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. If BE n was HIGH, then the appropriate Byte of DATA OUT for Qn + 2 would be disabled (High-Impedance state).
6."x" denotes Left or Right port. The diagram is with respect to that port.
Timing Waveform of Read Cycle for Flow-through Output (FT /PIPE
(1,2,6)
R/W
ADDRESS
DATA OUT
CE 0
CLK OE
CE 1
BE n
CE 0(B1)
ADDRESS (B1)
CLK
DATA OUT(B1)
ADDRESS (B2)
CE 0(B2)
DATA OUT(B2)
5687drw 07
(1,2)
NOTES:
1. B1 Represents Device #1; B2 Represents Device #
2. Each Device consists of one IDT70T3719/99M for this waveform, and are setup for depth expansion in this example. ADDRESS (B1) = ADDRESS (B2) in this situation.2. BE n , OE , and ADS = V IL ; CE 1(B1), CE 1(B2), R/W , CNTEN , and REPEAT = V IH .
Timing Waveform of a Multi-Device Flow-Through Read (1,2)
CE 0(B1)
ADDRESS (B1)
CLK
DATA OUT(B1)
ADDRESS (B2)
CE 0(B2)
DATA OUT(B2)
CLK "A"
R/W "A
"
ADDRESS "A"
DATA IN"A"
CLK "B"
R/W "B"
ADDRESS "B"
DATA OUT"B"
Timing Waveform of Left Port Write to Pipelined Right Port Read (1,2,4)
NOTES:
1.CE 0, BE n , and ADS = V IL ; CE 1, CNTEN , and REPEAT = V IH .
2.OE = V IL for Port "B", which is being read from. OE = V IH for Port "A", which is being written to.
3.If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
t CO + 2 t CYC2 + t CD2). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port will be t CO + t CYC2 + t CD2).
4.All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read (1,2,4)
DATA IN
"A"
CLK "B"
R/W "B"
ADDRESS "A"
R/W "A"
CLK "A"
ADDRESS "B"
DATA OUT "B"
NOTES:
1.CE 0, BE n, and ADS = V IL ; CE 1, CNTEN , and REPEAT = V IH .
2.OE = V IL for the Right Port, which is being read from. OE = V IH for the Left Port, which is being written to.
3.If t CO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be t CO + t CYC + t CD1). If t CO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will be t CO + t CD1).
4.All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
R/W
ADDRESS
DATA IN
CE 0
CLK
DATA OUT
CE 1
BE n
Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = V IL NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE 0, BE n , and ADS = V IL ; CE 1, CNTEN , and REPEAT = V IH . "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/W
ADDRESS
DATA IN
CE 0
CLK DATA OUT
CE 1
BE n
OE
(2)
NOTES:1.Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.2.CE 0, BE n , and ADS = V IL ; CE 1, CNTEN , and REPEAT = V IH .
3.Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
4.This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = V IL)(2)
(2) NOTES:
1.Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2.CE0, BE n, and ADS = V IL; CE1, CNTEN, and REPEAT = V IH.
3.Addresses do not have to be accessed sequentially since ADS = V IL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4."NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/W
ADDRESS
DATA IN
CE0
CLK
DATA OUT
CE1
BE n
R/W
ADDRESS
DATA IN
CE0
CLK
DATA OUT
CE1
BE n
OE
ADDRESS
CLK
DATA OUT ADS CNTEN
5687drw 15
Timing Waveform of Pipelined Read with Address Counter Advance (1)
NOTES:
1.CE 0, OE , BE n = V IL ; CE 1, R/W , and REPEAT = V IH .
2.If there is no address change via ADS = V IL (loading a new address) or CNTEN = V IL (advancing the address), i.e. ADS = V IH and CNTEN = V IH , then
the data output remains constant for subsequent clocks.
Timing Waveform of Flow-Through Read with Address Counter Advance (1)
ADDRESS
CLK
DATA OUT
ADS
CNTEN
5687drw 16
ADDRESS
COUNTER
ADDRESS
CLK
DATA IN R/W
REPEAT
5687drw 18
INTERNAL ADDRESS
ADS
CNTEN
ADDRESS
An
An+1
An+2
An+2
ADDRESS
An
DATA OUT
An+1
READ An+2
READ An+2
Timing Waveform of Write with Address Counter Advance (Flow-through or Pipelined Inputs) (1)
Timing Waveform of Counter Repeat (2,6)
ADDRESS
CLK
DATA IN
ADS
CNTEN
INTERNAL ADDRESS
NOTES:
1.CE 0, BE n , and R/W = V IL ; CE 1 and REPEAT = V IH .
2.CE 0, BE n = V IL ; CE 1 = V IH .
3.The "Internal Address" is equal to the "External Address" when ADS = V IL and equals the counter output when ADS = V IH .
4.No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.
https://www.doczj.com/doc/a06129710.html,TEN = V IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6.For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
Truth Table III — Interrupt Flag (1)
Left Port
Right Port Function
CLK L R/W L CE L A 17L -A 0L (3,4)INT L CLK R R/W R (2)
CE R (2)A 17R -A 0R (3,4)
INT R ?L L 3FFFF X ?X X X L Set Right INT R Flag ?X X X X ?X L 3FFFF H Reset Right INT R Flag ?X X X L ?L L 3FFFE X Set Left INT L Flag ?
H
L
3FFFE
H
?
X
X
X
X
Reset Left INT L Flag
5687 tbl 13
NOTES:
1.INT L and INT R must be initialized at power-up by Resetting the flags.
2.CE 0 = V IL and CE 1 = V IH . R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
3.A17X is a NC for IDT70T3799, therefore Interrupt Addresses are 1FFFF and 1FFFE.
4.Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Waveform of Interrupt Timing (2)
NOTES:
1.CE 0 = V IL and CE 1 = V IH
2.All timing is the same for Left and Right ports.
3.
Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
CLK R
CE R (1)
ADDRESS R (3)
CLK L
R/W L
ADDRESS L (3)
CE L (1)
5687drw 19
INT R
R/W R
COL R
COL L
(4)
CLK R
ADDRESS R
(4)
CLK L
ADDRESS L
Waveform of Collision Timing (1,2)
Both Ports Writing with Left Port Clock Leading
NOTES:
1.CE 0 = V IL , CE 1 = V IH .
2.For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3.Leading Port Output flag might output 3t CYC 2 + t COLS after Address match.
4.Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Collision Detection Timing (3,4)
Cycle Time
t OFS (ns)
Region 1 (ns) (1)
Region 2 (ns) (2)
5ns 0 - 2.8 2.81 - 4.66ns 0 - 3.8 3.81 - 5.67.5ns
0 - 5.3
5.31 - 7.1
56876 tbl 14
NOTES:1.Region 1
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.2.Region 2
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.3.All the production units are tested to midpoint of each region.4.These ranges are based on characterization of a typical device.
Left Port
Right Port Function
CLK L R/W L CE L A 17L -A 0L (2)COL L CLK R R/W R (1)
CE R (1)A 17R -A 0R (2)COL R ?H L MATCH H ?H L MATCH H Both ports reading. Not a valid collision.No flag output on either port ?H L MATCH L ?L L MATCH H Left port reading, Right port writing.Valid collision, flag output on Left port.?L L MATCH H ?H L MATCH L Right port reading, Left port writing.Valid collision, flag output on Right port.?
L
L
MATCH
L
?
L
L
MATCH
L
Both ports writing. Valid collision. Flag output on both ports.
5687 tbl 15
Truth Table IV — Collision Detection Flag
NOTES:
1.CE 0 = V IL and CE 1 = V IH . R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
2.Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
R/W
Timing Waveform - Entering Sleep Mode (1,2)
DAT A OUT
R/W
OE
Timing Waveform - Exiting Sleep Mode (1,2)
NOTES:
1.CE 1 = V IH.
2.All timing is same for Left and Right ports.
3.CE 0 has to be deactivated (CE 0 = V IH ) three cycles prior to asserting ZZ (ZZx = V IH ) and held for two cycles after asserting ZZ (ZZx = V IH ).
4.CE 0 has to be deactivated (CE 0 = V IH ) one cycle prior to de-asserting ZZ (ZZx = V IL ) and held for three cycles after de-asserting ZZ (ZZx = V IL ).
5.The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.