? Copyright 2006–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. PCI, PCI-X, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
Virtex-4Q FPGA Electrical Characteristics
Defense-grade Virtex?-4Q FPGAs are available in -10 speed grade and are qualified for industrial (T J =–40°C to +100°C), and military (T J =–55°C to +125°C) operational temperatures.Defense-grade Virtex-4Q FPGA DC and AC characteristics are specified for military and industrial grades only. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -10 speed grade military device are the same as for a -10 speed grade industrial device).
All supply voltage and junction temperature specifications are representative of worst-case conditions. The
parameters included are common to popular designs and typical applications.
This Defense-grade Virtex-4Q FPGA data sheet is part of an overall set of documentation on the Virtex-4 family of FPGAs available on the Xilinx website:?DS112, Virtex-4 Family Overview ?UG070, Virtex-4 FPGA User Guide ?UG071, Virtex-4 FPGA Configuration Guide ?UG073, XtremeDSP for Virtex-4 FPGAs User Guide ?UG075, Virtex-4 FPGA Packaging and Pinout Specification
?
UG072, Virtex-4 FPGA PCB Designer’s Guide
All specifications are subject to change without notice.
Virtex-4Q FPGA DC Characteristics
Virtex-4Q FPGA Data Sheet:DC and Switching Characteristics
DS595 (v1.6) April 27, 2010
Product Specification
Table 1:Absolute Maximum Ratings
Symbol Description
Values Units V CCINT Internal supply voltage relative to GND –0.5 to 1.32V V CCAUX Auxiliary supply voltage relative to GND –0.5 to 3.0V V CCO Output drivers supply voltage relative to GND –0.5 to 3.75V V BA TT Key memory battery backup supply –0.5 to 4.05V V REF Input reference voltage
–0.3 to 3.75V V IN
I/O input voltage relative to GND (all user and dedicated I/Os)
–0.75 to 4.05V I/O input voltage relative to GND (3) (restricted to maximum of 100 user I/Os)(4)–0.85 to 4.3V 2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)–0.75 to V CCO +0.5V V TS Voltage applied to 3-state 3.3V output (3) (all user and dedicated I/Os)
–0.75 to 4.05V Voltage applied to 3-state 3.3V output (3) (restricted to maximum of 100 user I/Os)(4)–0.85 to 4.3V 2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)–0.75 to V CCO +0.5
V V TRX T erminal receive supply voltage relative to GND –0.5 to 3.0V V TTX T erminal transmit supply voltage relative to GND –0.5 to 1.65V T STG Storage temperature (ambient)–65 to 150°C T SOL Maximum soldering temperature (2)+220°C T J Maximum junction temperature (2)
+125
°C
Notes:
1.Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2.For soldering guidelines and thermal considerations, see the Virtex-4 Packaging and Pinout Specification on the Xilinx website.
3.For 3.3V I/O operation, refer to the Virtex-4 FPGA User Guide , Chapter 6, 3.3V I/O Design Guidelines, T able 6-38.
4.
For more flexibility in specific designs, a maximum of 100 user I/Os can be stressed beyond the normal spec for no more than 20% of a data period. There are no bank restrictions.
Table 2:Recommended Operating Conditions
Symbol Description Min Max Units V CCINT Internal supply voltage relative to GND 1.14 1.26V V CCAUX Auxiliary supply voltage relative to GND 2.375 2.625V V CCO(1,2,3,4,5)Supply voltage relative to GND 1.14 3.45V
V IN 3.3V supply voltage relative to GND GND–0.20 3.45V 2.5V and below supply voltage relative to GND GND–0.20V CCO+0.2V
V BA TT(2)Battery voltage relative to GND 1.0 3.6V
Notes:
1.Configuration data is retained even if V CCO drops to 0V.
2.V BATT is required only when using bitstream encryption. If battery is not used, connect V BA TT to either ground or V CCAUX.
3.For 3.3V I/O operation, refer to the Virtex-4 FPGA User Guide.
4.Includes V CCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
5.The configuration output supply voltage V CC_CONFIG is also known as V CCO_0.
Table 3:DC Characteristics Over Recommended Operating Conditions
Symbol Description Min Typ Max Units
V DRINT Data retention V CCINT voltage
(below which configuration data might be lost)
0.9V
V DRI Data retention V CCAUX voltage
(below which configuration data might be lost)
2.0V
I REF V REF current per pin10μA I L Input or output leakage current per pin (sample-tested)10μA C IN Input capacitance (sample-tested)10pF
I RPU(1)Pad pull-up (when selected) @ V IN=0V, V CCO=3.3V5200μA Pad pull-up (when selected) @ V IN=0V, V CCO=3.0V5125μA Pad pull-up (when selected) @ V IN=0V, V CCO=2.5V5120μA Pad pull-up (when selected) @ V IN=0V, V CCO=1.8V560μA Pad pull-up (when selected) @ V IN=0V, V CCO=1.5V540μA
I RPD(1)Pad pull-down (when selected) @ V IN=V CCO5100μA I BA TT(1)Battery supply current75nA n T emperature diode ideality factor 1.02n
r Series resistance2Ω
Notes:
1.T ypical values are specified at nominal voltage, 25°C.
Table 4:Quiescent Supply Current
Symbol Description Device
Typ(1)
Max Units I-Grade M-Grade
I CCINTQ Quiescent V CCINT supply current
XQ4VLX25–139Note (4)mA XQ4VLX40121218Note (4)mA XQ4VLX60167301Note (4)mA XQ4VLX100292–Note (4)mA XQ4VLX160384–Note (4)mA XQ4VSX55271488Note (4)mA XQ4VFX60203365Note (4)mA
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current consumed depends on the power-on ramp rate of the power supply.
The power supplies can be turned on in any sequence, though the specifications shown in Table 5 are for the recommended
power-on sequence of V CCINT , V CCAUX , V CCO . Xilinx does not specify the current for other power-on sequences.
Table 5 shows the maximum current required by Virtex-4Q devices for proper power-on and configuration.
Once initialized and configured, use the XPOWER tool to estimate current drain on these supplies.
I CCOQ
Quiescent V CCO supply current
XQ4VLX25– 2.50Note (4)mA XQ4VLX40 1.25 2.50Note (4)mA XQ4VLX60
1.5 3.00Note (4)mA XQ4VLX100 1.75–Note (4)mA XQ4VLX160
2.5–Note (4)mA XQ4VSX55 1.5
3.00Note (4)mA XQ4VFX60 1.5 3.00Note (4)mA I CCAUXQ
Quiescent V CCAUX supply current
XQ4VLX25–54Note (4)mA XQ4VLX404365Note (4)mA XQ4VLX60
74111Note (4)mA XQ4VLX10095–Note (4)mA XQ4VLX160133–Note (4)mA XQ4VSX5591137Note (4)mA XQ4VFX60
80
120
Note (4)
mA
Notes:
1.T ypical values are specified at nominal voltage, 25°C.
2.T ypical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating.
3.
If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the Power Estimator or XPOWER tool.
4.
Use the XPower Estimator (XPE) tool to calculate maximum static power for specific process, voltage, and temperature conditions.
Table 4:Quiescent Supply Current (Cont’d)
Symbol
Description
Device Typ (1)
Max Units I-Grade M-Grade Table 5:Maximum Power-On Current for Virtex-4Q Devices
Device
I CCINT
I CCAUX
I CCO
Units Typ (1)Max (2)Typ (1)Max (2)Typ (1)Max (2)XQ4VLX2522028628555575390mA XQ4VLX40315315011070575390mA XQ4VLX603003960225825150390mA XQ4VLX100(3)58569123351050200450mA XQ4VLX160(3)85583255001238250600mA XQ4VSX555205355225930150450mA XQ4VFX60410
4680
220
1050
150
435
mA
Notes:
1.T ypical values are specified at nominal voltage, 25°C.
2.Maximum values are specified under worst-case process, voltage, and military temperature conditions.
3.
XQ4VLX100 and XQ4VLX160 are offered in I grade only. Values represent worst-case process, voltage and industrial temperature operating conditions.
SelectIO? DC Input and Output Levels
Values for V IL and V IH are recommended input voltages. Values for I OL and I OH are guaranteed over the recommended operating conditions at the V OL and V OH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum V CCO with the respective V OL and V OH voltage levels shown. Other standards are sample tested.Table 6:Power Supply Ramp Time
Symbol Description
Ramp Time Units V CCINT Internal supply voltage relative to GND 0.20 to 50.0ms V CCO Output drivers supply voltage relative to GND 0.20 to 50.0ms V CCAUX
Auxiliary supply voltage relative to GND
0.20 to 50.0
ms
Table 7:Select I/O DC Input and Output Levels
IOSTANDARD Attribute V IL
V IH
V OL
V OH I OL I OH V, Min V , Max V, Min V , Max V, Max V, Min mA
mA
LVTTL –0.20.8 2.0 3.450.4 2.4Note (3)Note (3)LVCMOS33–0.20.8 2.0 3.450.4V CCO –0.4Note (3)Note (3,6)
LVCMOS25–0.30.7 1.7V CCO +0.30.4V CCO –0.4Note (3)Note (3)LVCMOS18–0.335% V CCO 65% V CCO V CCO +0.30.4V CCO –0.45Note (4)Note (4)LVCMOS15–0.335% V CCO 65% V CCO V CCO +0.30.4V CCO –0.45Note (4)Note (4,6)PCI33_3(5)–0.230% V CCO 50% V CCO V CCO 10% V CCO 90% V CCO 1.5–0.5PCI66_3(5)–0.230% V CCO 50% V CCO V CCO 10% V CCO 90% V CCO 1.5–0.5PCI-X (5)–0.235% V CCO 50% V CCO V CCO 10% V CCO
90% V CCO
1.5–0.5GTLP –0.3V REF –0.1V REF +0.1–0.6N/A 36N/A GTL –0.3V REF –0.05V REF +0.05–0.4N/A 32N/A HSTL I (2)–0.3V REF –0.1V REF +0.1V CCO +0.30.4V CCO –0.48–8HSTL II (2)–0.3V REF –0.1V REF +0.1V CCO +0.30.4V CCO –0.416–16HSTL III (2)–0.3V REF –0.1V REF +0.1V CCO +0.30.4V CCO –0.424–8HSTL IV (2)–0.3V REF –0.1V REF +0.1V CCO +0.30.4V CCO –0.448–8DIFF HSTL II (2)–0.350% V CCO –0.150% V CCO +0.1V CCO +0.30.4V CCO –0.4––SSTL2I –0.3V REF –0.15V REF +0.15V CCO +0.3V TT –0.61V TT +0.618.1–8.1SSTL2II –0.3V REF –0.15V REF +0.15V CCO +0.3V TT –0.81
V TT +0.8116.2–16.2DIFF SSTL2II –0.350% V CCO –0.1550% V CCO +0.15V CCO +0.30.5V CCO –0.5––SSTL18I –0.3V REF –0.125V REF +0.125V CCO +0.3V TT –0.47V TT +0.47 6.7–6.7SSTL18II –0.3V REF –0.125
V REF +0.125
V CCO +0.3V TT –0.60
V TT +0.6013.4–13.4DIFF SSTL18II –0.3
50% V CCO –0.12550% V CCO +0.125
V CCO +0.3
0.4
V CCO –0.4
–
–
Notes:
1.T ested according to relevant specifications.
2.Applies to both 1.5V and 1.8V HSTL.
https://www.doczj.com/doc/b317368424.html,ing drive strengths of 2, 4, 6, 8, 12, 16, or 24mA.
https://www.doczj.com/doc/b317368424.html,ing drive strengths of 2, 4, 6, 8, 12, or 16mA.
5.For more information on PCI33_3, PCI66_3, and PCI-X refer to the Virtex-4 FPGA User Guide, SelectIO Resources , Chapter
6.6.
LVCMOS15 4mA, LVCMOS33 6mA, LVCMOS33 8mA have reduced drive strength (I OH ) by 20%.
LDT DC Specifications (LDT_25)
LVDS DC Specifications (LVDS_25)
Extended LVDS DC Specifications (LVDSEXT_25)
Table 8:LDT DC Specifications
Symbol DC Parameter
Conditions
Min Typ Max Units V CCO Supply Voltage
2.38 2.5 2.63V V OD Differential Output Voltage (1,2)R T = 100Ω across Q and Q signals 495600750mV Δ V OD Change in V OD Magnitude –1515mV V OCM Output Common Mode Voltage R T = 100Ω across Q and Q signals
495600715mV Δ V OCM Change in V OCM Magnitude –1515mV V ID Input Differential Voltage 2006001000mV Δ V ID Change in V ID Magnitude –1515mV V ICM Input Common Mode Voltage 440600
780mV Δ V ICM Change in V ICM Magnitude
–15
15
mV
Notes:
1.Recommended input maximum voltage not to exceed V CC0+0.2V .
2.
Recommended input minimum voltage not to go below –0.5V .
Table 9:LVDS DC Specifications
Symbol DC Parameter
Conditions
Min Typ Max Units V CCO Supply Voltage
2.38 2.5
2.63V V OH Output High Voltage for Q and Q R T = 100Ω across Q and Q signals 1.602
V V OL Output Low Voltage for Q and Q
R T = 100Ω across Q and Q signals
0.898V
V ODIFF Differential Output Voltage (1,2) (Q –Q),
Q = High (Q –Q), Q = High R T = 100Ω across Q and Q signals
247350550mV V OCM Output Common-Mode Voltage R T = 100Ω across Q and Q signals
1.100 1.250 1.375V V IDIFF Differential Input Voltage (Q –Q),Q = High (Q –Q), Q = High 100350600mV V ICM Input Common-Mode Voltage
0.3
1.2
2.2
V
Notes:
1.Recommended input maximum voltage not to exceed V CC0+0.2V .
2.
Recommended input minimum voltage not to go below –0.5V .
Table 10:Extended LVDS DC Specifications Symbol DC Parameter
Conditions Min
Typ
Max
Units
V CCO Supply Voltage
2.38 2.5 2.63V V OH Output High Voltage for Q and Q R T = 100Ω across Q and Q signals –– 1.785V V OL Output Low Voltage for Q and Q R T = 100Ω across Q and Q signals 0.715––V V ODIFF Differential Output Voltage (Q –Q),Q = High (Q –Q), Q = High R T = 100Ω across Q and Q signals 380–820mV V OCM Output Common-Mode Voltage R T = 100Ω across Q and Q signals 1.000 1.250 1.375V V IDIFF Differential Input Voltage (1,2) (Q –Q),Q = High (Q –Q), Q = High Common-mode input voltage = 1.25V 100–1000mV V ICM
Input Common-Mode Voltage
Differential input voltage =±350mV
0.3
1.2
2.2
V
Notes:
1.Recommended input maximum voltage not to exceed V CC0+0.2V .
2.Recommended input minimum voltage not to go below –0.5V .
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100Ω differential load only, for example, a 100Ω resistor between the two receiver pins. The V OH levels are 200mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL , see the Virtex-4 FPGA User Guide , Chapter 6, SelectIO Resources.
Table 11:LVPECL DC Specifications
Symbol DC Parameter
Min Typ Max Units
V OH Output High Voltage V CC –1.025 1.545V CC –0.88V V OL Output Low Voltage
V
CC –1.81
0.795
V CC –1.62
V V ICM Input Common-Mode Voltage 0.6 2.2V V IDIFF Differential Input Voltage (1,2)
0.100
1.5
V
Notes:
1.Recommended input maximum voltage not to exceed V CC0+0.2V .
2.
Recommended input minimum voltage not to go below –0.5V .
Figure 1:Single-Ended Output Voltage Swing
Figure 2:Peak-to-Peak Differential Output Voltage
Interface Performance Characteristics Table 12:Interface Performances
Description Speed Grade
-10
Networking Applications
SFI-4.1 (SDR LVDS Interface)(1,7)644MHz SPI-4.2 (DDR LVDS Interface)(2)800Mb/s Memory Interfaces
DDR(3)426Mb/s DDR2(4)510Mb/s QDR II SRAM(5)514Mb/s RLDRAM II(6)524Mb/s
Notes:
1.Performance defined using design implementation described in application note XAPP704, Virtex-4 High-Speed SDR LVDS T ransceiver.
2.Performance defined using design implementation described in application note XAPP700, Dynamic Phase Alignment for Networking
Applications or XAPP705, Virtex-4 High-Speed DDR LVDS Transceiver.
3.Performance defined using design implementation described in application note XAPP709, DDR SDRAM Controller Using Virtex-4 Devices.
4.Performance defined using design implementation described in application note XAPP702, DDR2 Controller Using Virtex-4 Devices.
5.Performance defined using design implementation described in application note XAPP703, QDR II SRAM Interface for Virtex-4 Devices.
6.Performance defined using design implementation described in application note XAPP710, Synthesizable CIO DDR RLDRAM II Controller
for Virtex-4 FPGAs.
7.Maximum frequency of 500MHz for operation beyond industrial temperature range.
Switching Characteristics
Switching characteristics are specified on a per-speed- grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows:
Advance
These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur.
Preliminary
These specifications are based on complete ES (engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data.
Production
These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades.
Table13 correlates the current status of each Virtex-4Q device with a corresponding speed specification version 1.67 designation.Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device.
All specifications are always representative of worst-case supply voltage and junction temperature conditions. Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-4 FPGAs.
Table 13:Virtex-4Q Device Speed Grade Designations Device
Speed Grade Designations
Advance Preliminary Production XQ4VLX25 -10(M)
XQ4VLX40-10(M) -10(I)
XQ4VLX60 -10(M)
XQ4VLX100 -10(I)
XQ4VLX160 -10(I)
XQ4VSX55 -10(M)
XQ4VFX60-10(M) -10(I)
PowerPC Switching Characteristics
Consult UG018, PowerPC? 405 Processor Block Reference Guide for further information. Table 14:PowerPC 405 Processor Clocks Absolute AC Characteristics
Description
Speed Grade
Units -10
Min Max
Characteristics when APU Not Used
CPMC405CLOCK frequency(1,4)0350MHz CPMDCRCLK(3)0350MHz CPMFCMCLK(3)––MHz JTAGC405TCK frequency(2)0175MHz PLBCLK(3)0350MHz BRAMDSOCMCLK(3)0350MHz BRAMISOCMCLK(3)0350MHz Characteristics when APU Used
CPMC405CLOCK frequency(1,4)0233MHz CPMDCRCLK(3)0233MHz CPMFCMCLK(3)0233MHz JTAGC405TCK frequency(2)0116.5MHz PLBCLK(3)0233MHz BRAMDSOCMCLK(3)0233MHz BRAMISOCMCLK(3)0233MHz Notes:
1.Worst-case DCM output clock jitter is included in these specifications.
2.The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is system dependent,
and will be much less.
3.The theoretical maximum frequency of these clocks is equal to the CPMC405CLOCK. Integer clock ratios are required for the
CPMC405CLOCK and BRAMDSOCMCLK, CPMC405CLOCK and BRAMISOCMCLK, CPMC405CLOCK and CPMDCRCLK,
CPMC405CLOCK and CPMFCMCLK, and CPMC405CLOCK and PLBCLK. The integer ratios can be different for each interface. However, the achievable maximum is system dependent.
4.Maximum operating frequency of CPMC405CLOCK is specified with the input pin TIEC405DISOPERANDFWD connected to a logic1.
Table 15:Processor Block Switching Characteristics
Description Symbol Speed
Grade Units -10
Setup and Hold Relative to Clock (CPMC405CLOCK)
Clock and Power Management control inputs T PPCDCK_CORECKI
T PPCCKD_CORECKI 0.74
0.23
ns Min
Reset control inputs T PPCDCK_RSTCHIP
T PPCCKD_RSTCHIP 0.74
0.23
ns Min
Debug control inputs T PPCDCK_EXBUSHAK
T PPCCKD_EXBUSHAK 0.74
0.23
ns Min
Trace control inputs T PPCDCK_TRCDIS
T PPCCKD_TRCDIS 0.74
0.23
ns Min
External Interrupt Controller control inputs T PPCDCK_CINPIRQ
T PPCCKD_CINPIRQ 1.40
0.23
ns Min
Clock to Out
Clock and Power Management control outputs T PPCCKO_CORESLP 1.74ns Max Reset control outputs T PPCCKO_RSTCHIP 1.83ns Max Debug control outputs T PPCCKO_DBGLDAPU 1.70ns Max Trace control outputs T PPCCKO_TRCCYCLE 1.83ns Max Clock
CPMC405CLOCK minimum pulse width, High T CPWH 1.43ns Min CPMC405CLOCK minimum pulse width, Low T CPWL 1.43ns Min
Table 16:Processor Block PLB Switching Characteristics
Description Symbol Speed
Grade Units -10
Setup and Hold Relative to Clock (PLBCLK)
Processor Local Bus (ICU/DCU) control inputs T PPCDCK_ICUBUSY
T PPCCKD_ICUBUSY 0.76
0.23
ns Min
Processor Local Bus (ICU/DCU) data inputs T PPCDCK_ICURDDB
T PPCCKD_ICURDDB 1.15
0.23
ns Min
Clock to Out
Processor Local Bus (ICU/DCU) control outputs T PPCCKO_DCUABORT 2.05ns Max Processor Local Bus (ICU/DCU) address bus outputs T PPCCKO_ICUABUS 2.13ns Max Processor Local Bus (ICU/DCU) data bus outputs T PPCCKO_DCUWRDBUS 2.57ns Max Table 17:Processor Block JTAG Switching Characteristics
Description Symbol Speed
Grade Units -10
Setup and Hold Relative to Clock (JTAGC405TCK)
JTAG control inputs T PPCDCK_JTGTDI
T PPCCKD_JTGTDI 1.48
0.23
ns Min
JTAG reset input T PPCDCK_JTGTRSTN
T PPCCKD_JTGTRSTN 0.74
0.23
ns Min
Clock to Out
JTAG control outputs T PPCCKO_JTGTDO 2.14ns Max
Table 18:PowerPC 405 Data-Side On-Chip Memory Switching Characteristics
Description Symbol Speed
Grade Units -10
Setup and Hold Relative to Clock (BRAMDSOCMCLK)
Data-Side On-Chip Memory data bus inputs T PPCDCK_DSOCMRDDB
T PPCCKD_DSOCMRDDB 0.74
0.23
ns Min
Clock to Out
Data-Side On-Chip Memory control outputs T PPCCKO_BRAMBWR 2.65ns Max Data-Side On-Chip Memory address bus outputs T PPCCKO_BRAMABUS 2.65ns Max Data-Side On-Chip Memory data bus outputs T PPCCKO_IBRAMWRDBUS01 2.06ns Max
Table 19:PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics
Description Symbol Speed
Grade Units -10
Setup and Hold Relative to Clock (BRAMISOCMCLK)
Instruction-Side On-Chip Memory data bus inputs T PPCDCK_ISOCMRDDB
T PPCCKD_ISOCMRDDB 0.94
0.23
ns Min
Clock to Out
Instruction-Side On-Chip Memory control outputs T PPCCKO_IBRAMEN 3.88ns Max Instruction-Side On-Chip Memory address bus outputs T PPCCKO_IBRAMRDABUS 2.13ns Max Instruction-Side On-Chip Memory data bus outputs T PPCCKO_IBRAMWRDBUS 2.14ns Max
Table 20:Processor Block DCR Bus Switching Characteristics
Description Symbol Speed
Grade Units -10
Setup and Hold Relative to Clock (CPMDCRCLOCK)
Device Control Register Bus control inputs T PPCDCK_EXDCRACK
T PPCCKD_EXDCRACK 0.15
0.19
ns Min
Device Control Register Bus data inputs T PPCDCK_EXDCRDBUSI
T PPCCKD_EXDCRDBUSI 1.02
0.27
ns Min
Clock to Out
Device Control Register Bus control outputs T PPCCKO_EXDCRRD 1.54ns Max Device Control Register Bus address bus outputs T PPCCKO_EXDCRABUS 1.66ns Max Device Control Register Bus data bus outputs T PPCCKO_EXDCRDBUSO 1.67ns Max
Table 21:Processor Block APU Interface Switching Characteristics
Description Symbol Speed
Grade Units -10
Setup and Hold Relative to Clock (CPMDFCMCLOCK)
APU bus control inputs T PPCDCK_DCDCREN
T PPCCKD_DCDCREN 0.42
0.23
ns Min
APU bus data inputs T PPCDCK_RESULT
T PPCCKD_RESULT 0.78
0.23
ns Min
Clock to Out
APU bus control outputs T PPCCKO_APUFCMDEC 2.00ns Max APU bus data outputs T PPCCKO_RADAT A 2.00ns Max
IOB Pad Input/Output/3-State Switching Characteristics
Table22, page12 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard and 3-state delays. T IOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO? input buffer. T IOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer.T IOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer.
Table24, page17 summarizes the value of T IOTPHZ.
T IOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (for example, a high-impedance state).
Table 22:IOB Switching Characteristics(1,2)
IOSTANDARD Attribute(1)
Speed Grade
Units
-10
T IOPI T IOOP T IOTP
LVDS_25 1.28 1.85 1.85ns RSDS_25 1.28 1.85 1.85ns LVDSEXT_25 1.30 1.91 1.91ns LDT_25 1.28 1.82 1.82ns BLVDS_25 1.28 2.34 2.34ns ULVDS_25 1.28 1.83 1.83ns PCI33_3 (PCI?, 33MHz, 3.3V)0.97 3.02 3.02ns PCI66_3 (PCI, 66MHz, 3.3V)0.97 2.72 2.72ns PCI-X (PCI-X)0.97 2.25 2.25ns GTL 1.63 2.03 2.03ns GTLP 1.68 2.03 2.03ns HSTL_I 1.64 2.35 2.35ns HSTL_II 1.64 2.13 2.13ns HSTL_III 1.64 2.22 2.22ns HSTL_IV 1.64 2.03 2.03ns HSTL_I _18 1.60 2.21 2.21ns HSTL_II _18 1.60 2.16 2.16ns HSTL_III _18 1.60 2.09 2.09ns HSTL_IV_18 1.60 2.06 2.06ns SSTL2_I 1.68 2.43 2.43ns SSTL2_II 1.68 2.16 2.16ns LVTTL, Slow, 2mA0.977.037.03ns LVTTL, Slow, 4mA0.97 5.04 5.04ns LVTTL, Slow, 6mA0.97 4.91 4.91ns LVTTL, Slow, 8mA0.97 4.91 4.91ns LVTTL, Slow, 12mA0.97 3.96 3.96ns LVTTL, Slow, 16mA0.97 3.46 3.46ns LVTTL, Slow, 24mA0.97 3.12 3.12ns LVTTL, Fast, 2mA0.97 4.86 4.86ns LVTTL, Fast, 4mA0.97 3.46 3.46ns LVTTL, Fast, 6mA0.97 3.00 3.00ns
LVTTL, Fast, 8mA 0.97 2.79 2.79ns LVTTL, Fast, 12mA 0.97 2.47 2.47ns LVTTL, Fast, 16mA 0.97 2.47 2.47ns LVTTL, Fast, 24mA 0.97 2.20 2.20ns LVCMOS33, Slow, 2mA 0.978.738.73ns LVCMOS33, Slow, 4mA 0.97 6.09 6.09ns LVCMOS33, Slow, 6mA 0.97 5.00 5.00ns LVCMOS33, Slow, 8mA 0.97 3.95 3.95ns LVCMOS33, Slow, 12mA 0.97 3.42 3.42ns LVCMOS33, Slow, 16mA 0.97 2.49 2.49ns LVCMOS33, Slow, 24mA 0.97 2.49 2.49ns LVCMOS33, Fast, 2mA 0.977.447.44ns LVCMOS33, Fast, 4mA 0.97 4.33 4.33ns LVCMOS33, Fast, 6mA 0.97 3.55 3.55ns LVCMOS33, Fast, 8mA 0.97 2.46 2.46ns LVCMOS33, Fast, 12mA 0.97 2.27 2.27ns LVCMOS33, Fast, 16mA 0.97 2.08 2.08ns LVCMOS33, Fast, 24mA 0.97 2.08 2.08ns LVCMOS25, Slow, 2mA 0.88 5.89 5.89ns LVCMOS25, Slow, 4mA 0.88 5.02 5.02ns LVCMOS25, Slow, 6mA 0.88 4.31 4.31ns LVCMOS25, Slow, 8mA 0.88 4.31 4.31ns LVCMOS25, Slow, 12mA 0.88 3.50 3.50ns LVCMOS25, Slow, 16mA 0.88 3.31 3.31ns LVCMOS25, Slow, 24mA 0.88 2.77 2.77ns LVCMOS25, Fast, 2mA 0.88 3.89 3.89ns LVCMOS25, Fast, 4mA 0.88 3.19 3.19ns LVCMOS25, Fast, 6mA 0.88 2.81 2.81ns LVCMOS25, Fast, 8mA 0.88 2.52 2.52ns LVCMOS25, Fast, 12mA 0.88 2.43 2.43ns LVCMOS25, Fast, 16mA 0.88 2.21 2.21ns LVCMOS25, Fast, 24mA 0.88 2.13 2.13ns LVCMOS18, Slow, 2mA 1.25 5.89 5.89ns LVCMOS18, Slow, 4mA 1.25 4.35 4.35ns LVCMOS18, Slow, 6mA 1.25 4.00 4.00ns LVCMOS18, Slow, 8mA 1.25 3.76 3.76ns LVCMOS18, Slow, 12mA 1.25 3.74 3.74ns LVCMOS18, Slow, 16mA 1.25 3.55 3.55ns LVCMOS18, Fast, 2mA 1.25 3.89 3.89ns LVCMOS18, Fast, 4mA 1.25 3.02 3.02ns LVCMOS18, Fast, 6mA 1.25 2.72 2.72ns LVCMOS18, Fast, 8mA 1.25
2.52
2.52
ns
IOSTANDARD Attribute (1)
Units
-10T IOPI
T IOOP T IOTP
LVCMOS18, Fast, 12mA 1.25 2.36 2.36ns LVCMOS18, Fast, 16mA 1.25 2.27 2.27ns LVCMOS15, Slow, 2mA 1.34 6.61 6.61ns LVCMOS15, Slow, 4mA 1.34 4.88 4.88ns LVCMOS15, Slow, 6mA 1.34 4.26 4.26ns LVCMOS15, Slow, 8mA 1.34 4.26 4.26ns LVCMOS15, Slow, 12mA 1.34 3.77 3.77ns LVCMOS15, Slow, 16mA 1.34 3.53 3.53ns LVCMOS15, Fast, 2mA 1.34 4.17 4.17ns LVCMOS15, Fast, 4mA 1.34 3.32 3.32ns LVCMOS15, Fast, 6mA 1.34 2.94 2.94ns LVCMOS15, Fast, 8mA 1.34 2.71 2.71ns LVCMOS15, Fast, 12mA 1.34 2.50 2.50ns LVCMOS15, Fast, 16mA 1.34 2.43 2.43ns LVDCI_330.97 3.13 3.13ns LVDCI_250.88 3.02 3.02ns LVDCI_18 1.25 2.95 2.95ns LVDCI_15 1.34 2.93 2.93ns LVDCI_DV2_250.88 2.27 2.27ns LVDCI_DV2_18 1.25 2.28 2.28ns LVDCI_DV2_15 1.34 2.58 2.58ns GTL_DCI 1.51 2.03 2.03ns GTLP_DCI 1.23 2.03 2.03ns HSTL_I_DCI 1.64 2.35 2.35ns HSTL_II_DCI 1.64 2.13 2.13ns HSTL_III_DCI 1.64 2.22 2.22ns HSTL_IV_DCI 1.64 2.03 2.03ns HSTL_I_DCI_18 1.60 2.21 2.21ns HSTL_II_DCI_18 1.60 2.16 2.16ns HSTL_III_DCI_18 1.60 2.09 2.09ns HSTL_IV_DCI_18 1.60 2.06 2.06ns SSTL2_I_DCI 1.68 2.46 2.46ns SSTL2_II_DCI 1.68 2.45 2.45ns LVPECL_25 1.77 1.74 1.74ns SSTL18_I 1.68 2.54 2.54ns SSTL18_II 1.68 2.24 2.24ns SSTL18_I_DCI 1.68 2.32 2.32ns SSTL18_II_DCI 1.68
2.18
2.18
ns
Notes:
1.The I/O standard is selected in the Xilinx ISE? software using the IOSTANDARD attribute.
2.
All I/O timing specifications are measured with V CCO at –5% from nominal.
IOSTANDARD Attribute (1)
Units
-10T IOPI
T IOOP T IOTP
Table 23:T IOOP and T IOTP Offset for 125°C Operation
IOSTANDARD Attribute
Speed Grade
Units
-10
I-Grade M-Grade Delta
LVDS 1.85 2.230.38ns RSDS 1.85 2.230.38ns LVDSEXT 1.91 2.250.34ns LDT 1.82 2.230.41ns PCI33_3 3.02 3.260.24ns PCI66_3 2.72 3.260.54ns PCIX 2.25 2.490.24ns GTL 2.03 2.270.24ns GTLP 2.03 2.250.22ns HSTL_I 2.35 2.540.19ns HSTL_II 2.13 2.470.34ns HSTL_III 2.22 2.550.33ns HSTL_IV 2.03 2.430.40ns HSTL_I_18 2.21 2.430.22ns HSTL_II_18 2.16 2.390.23ns HSTL_III_18 2.09 2.400.31ns HSTL_IV_18 2.06 2.380.32ns SSTL2_I 2.43 2.460.03ns SSTL2_II 2.16 2.270.11ns LVTTL_S27.039.95 2.92ns LVTTL_S4 5.047.84 2.80ns LVTTL_S6 4.91 6.67 1.76ns LVTTL_S8 4.91 6.40 1.49ns LVTTL_S12 3.96 4.870.91ns LVTTL_S16 3.46 4.420.96ns LVTTL_S24 3.12 3.240.12ns LVTTL_F2 4.868.44 3.58ns LVTTL_F4 3.46 6.41 2.95ns LVTTL_F6 3.00 4.76 1.76ns LVTTL_F8 2.79 3.97 1.18ns LVTTL_F12 2.47 2.920.45ns LVTTL_F16 2.47 2.930.46ns LVTTL_F24 2.20 2.870.67ns LVCMOS33_S28.7311.43 2.70ns LVCMOS33_S4 6.098.56 2.47ns LVCMOS33_S6 5.007.27 2.27ns LVCMOS33_S8 3.95 6.35 2.40ns LVCMOS33_S12 3.42 4.74 1.32ns
LVCMOS33_S16 2.49 4.56 2.07ns LVCMOS33_S24 2.49 3.060.57ns LVCMOS33_F27.4410.18 2.74ns LVCMOS33_F4 4.33 6.18 1.85ns LVCMOS33_F6 3.55 5.53 1.98ns LVCMOS33_F8 2.46 4.47 2.01ns LVCMOS33_F12 2.27 3.220.95ns LVCMOS33_F16 2.08 2.740.66ns LVCMOS33_F24 2.08 2.610.53ns LVCMOS25_S2 5.898.57 2.68ns LVCMOS25_S4 5.02 6.44 1.42ns LVCMOS25_S6 4.31 6.00 1.69ns LVCMOS25_S8 4.31 5.240.93ns LVCMOS25_S12 3.50 4.300.80ns LVCMOS25_S16 3.31 3.950.64ns LVCMOS25_S24 2.77 2.64-0.13ns LVCMOS25_F2 3.897.97 4.08ns LVCMOS25_F4 3.19 4.99 1.80ns LVCMOS25_F6 2.81 3.92 1.11ns LVCMOS25_F8 2.52 3.290.77ns LVCMOS25_F12 2.43 2.430.00ns LVCMOS25_F16 2.21 2.390.18ns LVCMOS25_F24 2.13 2.390.26ns LVCMOS18_S2 5.898.68 2.79ns LVCMOS18_S4 4.357.31 2.96ns LVCMOS18_S6 4.00 5.66 1.66ns LVCMOS18_S8 3.76 5.11 1.35ns LVCMOS18_S12 3.74 4.590.85ns LVCMOS18_S16 3.55 3.890.34ns LVCMOS18_F2 3.898.34 4.45ns LVCMOS18_F4 3.02 5.99 2.97ns LVCMOS18_F6 2.72 4.35 1.63ns LVCMOS18_F8 2.52 3.66 1.14ns LVCMOS18_F12 2.36 2.800.44ns LVCMOS18_F16 2.27 2.700.43ns LVCMOS15_S2 6.619.21 2.60ns LVCMOS15_S4 4.887.75 2.87ns LVCMOS15_S6
4.26
6.14
1.88
ns IOSTANDARD Attribute
Units
-10
I-Grade M-Grade
Delta
Ethernet MAC Switching Characteristics
Consult UG074,Virtex-4 FPGA Embedded T ri-Mode Ethernet MAC User Guide for further information.Input/Output Logic Switching Characteristics
LVCMOS15_S8 4.26 6.18 1.92ns LVCMOS15_S12 3.77 4.77 1.00ns LVCMOS15_S16 3.53 4.070.54ns LVCMOS15_F2 4.178.32 4.15ns LVCMOS15_F4 3.32 6.53 3.21ns LVCMOS15_F6 2.94 4.69 1.75ns LVCMOS15_F8 2.71 3.90 1.19ns LVCMOS15_F12 2.50 2.920.42ns LVCMOS15_F16 2.43 2.840.41ns SSTL18_I 2.54 2.44-0.10ns SSTL18_II
2.24
2.42
0.18
ns Table 24:IOB 3-State On Output Switching Characteristics (T IOTPHZ )
Symbol
Description
Speed Grade
Units -10T IOTPHZ
T input to Pad high-impedance
1.12
ns
Table 25:Maximum Ethernet MAC Performance
Description
Speed Grade
Units -10Ethernet MAC Maximum Performance
10/100/1000
Mb/s
Table 26:ILOGIC Switching Characteristics
Symbol
Description
Speed Grade
Units
-10
Setup/Hold T ICE1CK /T ICKCE1CE1 pin setup/hold with respect to CLK 0.79/–0.23ns T ICECK /T ICKCE DL YCE pin setup/hold with respect to CLKDIV 0.23/0.16ns T IRSTCK /T ICKRST DL YRST pin setup/hold with respect to CLKDIV –0.02/0.54ns T IINCCK /T ICKINC DL YINC pin setup/hold with respect to CLKDIV 0.01/0.51ns T ISRCK /T ICKSR SR/REV pin setup/hold with respect to CLK 1.59/–0.56ns T IDOCK /T IOCKD D pin setup/hold with respect to CLK without Delay 0.34/–0.10ns T IDOCKD /T IOCKDD
D pin setup/hold with respect to CLK (IOBDELAY_TYP
E =DEFAULT)
8.84/–5.99ns D pin setup/hold with respect to CLK
(IOBDELAY_TYPE =FIXED, IOBDELAY_VALUE =0)
1.09/–0.63
ns
IOSTANDARD Attribute
Units
-10
I-Grade M-Grade
Delta
Combinatorial T IDI
D pin to O pin propagation delay, no Delay 0.24ns T IDID
D pin to O pin propagation delay (IOBDELAY_TYP
E =DEFAULT)
7.96ns D pin to O pin propagation delay
(IOBDELAY_TYPE =FIXED, IOBDELAY_VALUE =0)
0.99
ns
Sequential Delays T IDLO
D pin to Q1 pin using flip-flop as a latch without Delay 0.71ns T IDLOD
D pin to Q1 pin using flip-flop as a latch (IOBDELAY_TYP
E =DEFAULT)
9.21ns D pin to Q1 pin using flip-flop as a latch
(IOBDELAY_TYPE =FIXED, IOBDELAY_VALUE =0) 1.45ns T ICKQ CLK to Q outputs
0.72ns T ICE1Q CE1 pin to Q1 using flip-flop as a latch, propagation delay 1.27ns T RQ SR/REV pin to OQ/TQ out 2.44ns T GSRQ
Global Set/Reset to Q outputs
2.03
ns
Set/Reset T RPW
Minimum Pulse Width, SR/REV inputs
0.70
ns, Min
Table 27:OLOGIC Switching Characteristics
Symbol
Description
Speed Grade
Units
-10
Setup/Hold T ODCK /T OCKD D1/D2 pins setup/hold with respect to CLK 0.75/–0.22ns T OOCECK /T OCKOCE OCE pin setup/hold with respect to CLK 0.77/–0.33ns T OSRCK /T OCKSR SR/REV pin setup/hold with respect to CLK 1.42/–0.55ns T OTCK /T OCKT T1/T2 pins setup/hold with respect to CLK 0.75/–0.22ns T OTCECK /T OCKTCE
TCE pin setup/hold with respect to CLK
0.77/–0.33
ns
Combinatorial T ODQ D1 to OQ out 0.76ns T OTQ
T1 to TQ out
0.76
ns
Sequential Delays T IOSRON REV pin to TQ out 1.64ns T OCKQ CLK to OQ/TQ out 0.59ns T RQ SR/REV pin to OQ/TQ out 1.64ns T GSRQ
Global Set/Reset to Q outputs
2.03
ns
Set/Reset T RPW
Minimum Pulse Width, SR/REV inputs
0.70
ns Min
Table 26:ILOGIC Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
Units
-10
Input Serializer/Deserializer Switching Characteristics Table 28:ISERDES Switching Characteristics
Symbol Description Speed Grade
Units -10
Setup/Hold for Control Lines
T ISCCK_BITSLIP/T ISCKC_BITSLIP BITSLIP pin setup/hold with respect to CLKDIV0.40/–0.13ns T ISCCK_CE/T ISCKC_CE(2)CE pin setup/hold with respect to CLK (for CE1) 0.69/–0.25ns T ISCCK_CE2/T ISCKC_CE2(2)CE pin setup/hold with respect to CLKDIV (for CE2)0.16/–0.02ns T ISCCK_DL YCE/T ISCKC_DL YCE DL YCE pin setup/hold with respect to CLKDIV0.23/0.16ns T ISCCK_DL YINC/T ISCKC_DL YINC DL YINC pin setup/hold with respect to CLKDIV0.01/0.51ns T ISCCK_DL YRST/T ISCKC_DL YRST DL YRST pin setup/hold with respect to CLKDIV–0.02/0.54ns T ISCCK_REV REV pin setup with respect to CLK 1.23ns T ISCCK_SR SR pin setup with respect to CLKDIV0.92ns Setup/Hold for Data Lines
T ISDCK_D/T ISCKD_D D pin setup/hold with respect to CLK
(IOBDELAY=IBUF or NONE)
0.34/–0.11ns
D pin setup/hold with respect to CLK
(IOBDELAY=IFD or BOTH,
IOBDELAY_TYPE=DEFAULT)
8.84/–6.51ns
D pin setup/hold with respect to CLK(1)
(IOBDELAY=IFD or BOTH,
IOBDELAY_TYPE=FIXED, IOBDELAY_VALUE=0)
1.08/–0.68ns
T ISDCK_DDR/T ISCKD_DDR D pin setup/hold with respect to CLK at DDR mode
(IOBDELAY=IBUF or NONE)
0.34/–0.11ns
D pin setup/hold with respect to CLK at DDR mode
(IOBDELAY=IFD or BOTH,
IOBDELAY_TYPE=DEFAULT)
8.84/–6.51ns
D pin setup/hold with respect to CLK at DDR mode(1)
(IOBDELAY=IFD or BOTH,
IOBDELAY_TYPE=FIXED, IOBDELAY_VALUE=0)
1.08/–0.68ns
Sequential Delays
T ISCKO_Q CLKDIV to out at Q pin0.85ns Propagation Delays
T ISDO_DO_IOBDELAY_IFD D input to DO output pin (IOBDELAY=IFD)0.24ns T ISDO_DO_IOBDELAY_NONE D input to DO output pin (IOBDELAY=NONE)0.24ns
T ISDO_DO_IOBDELAY_BOTH D input to DO output pin(IOBDELAY=BOTH,
IOBDELAY_TYPE=DEFAULT)
7.96ns
D input to DO output pin(1) (IOBDELAY=BOTH,
IOBDELAY_TYPE=FIXED, IOBDELAY_VALUE=0)
0.99ns
T ISDO_DO_IOBDELAY_IBUF D input to DO output pin(IOBDELAY=IBUF,
IOBDELAY_TYPE=DEFAULT)
7.96ns
D input to DO output pin(1) (IOBDELAY=IBUF,
IOBDELAY_TYPE=FIXED, IOBDELAY_VALUE=0)
0.99ns
Notes:
1.Recorded at 0 tap value.
2.T ISCCK_CE2 and T ISCKC_CE2 are reported as T ISCCK_CE/T ISCKC_CE in TRCE report.
Input Delay Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 29:Input Delay Switching Characteristics
Symbol
Description
Speed Grade
Units -10T IDELAYRESOLUTION IDELAY Chain Delay Resolution 75
ps T IDELAYTOT AL_ERR Cumulative delay at a given tap (3)
[(tap ?1)x 75+34] ±0.07[(tap ?1)x
75+34]
ps T IDELAYCTRLCO_RDY Reset to Ready for IDELAYCTRL (Maximum) 3.00μs F IDELAYCTRL_REF
REFCLK frequency 200MHz IDELAYCTRL_REF_PRECISION (2)
REFCLK precision ±10MHz T IDELAYCTRL_RPW
Minimum Reset pulse width
50.0ns T IDELAYP AT_JIT
Pattern dependent period jitter in delay chain for clock pattern
0Note (1)
Pattern dependent period jitter in delay chain for random data pattern (PRBS 23)
10±2
Note (1)
Notes:
1.Units in ps peak-to-peak per tap.
2.See the “REFCLK - Reference Clock”section (specific to IDELAYCTRL) in the Virtex-4 FPGA User Guide , Chapter 7, SelectIO Logic Resources .
3.
This value accounts for tap 0, an anomaly in the tap chain with an average value of 34ps.
Table 30:OSERDES Switching Characteristics
Symbol
Description
Speed Grade
Units
-10
Setup/Hold T OSDCK_D /T OSCKD_D D input setup/hold with respect to CLKDIV 0.50/–0.03ns T OSDCK_T /T OSCKD_T (1)T input setup/hold with respect to CLK 0.62/–0.16ns T OSDCK_T2/T OSCKD_T2(1)T input setup/hold with respect to CLKDIV 0.50/–0.03ns T OSCCK_OCE /T OSCKC_OCE OCE input setup/hold with respect to CLK 0.64/0.03ns T OSCCK_S
SR (Reset) input setup with respect to CLKDIV 0.96ns T OSCCK_TCE /T OSCKC_TCE
TCE input setup/hold with respect to CLK
0.64/0.03
ns
Sequential Delays T OSCKO_OQ Clock to out from CLK to OQ 0.59ns T OSCKO_TQ
Clock to out from CLK to TQ
0.59
ns
Combinatorial T OSDO_TTQ T input to TQ Out
0.76ns T OSCO_OQ Asynchronous Reset to OQ 1.64ns T OSCO_TQ Asynchronous Reset to TQ
1.64
ns
Notes:
1.
T OSDCK_T2 and T OSCKD_T2 are reported as T OSDCK_T /T OSCKD_T in TRCE report.