This specification is subject to change without notice. Silicon Integrated Systems Corporation assumes no
responsibility for any errors contained herein.
Copyright by Silicon Integrated Systems Corp., all rights reserved.
SiS 740 / 961
Design and Guide
Preliminary Rev. 0.3 Aug. 6, 2001
Contents
1 INTRODUCTION (4)
2 MOTHERBOARD CONSIDERA TION (6)
2.1 Placement Design (6)
2.2 SiS Chipset Design (8)
2.3 BGA Component Layout Guideline (10)
2.4 AMD Socket A CPU Design (17)
2.5 SDRAM Design (22)
2.6 CLK Routing Guideline (24)
2.7 SIS740 GUI, VGA Signals and V-DIMM Design (25)
2.7.1 VGA Layout Rules (25)
2.7.2 SiS740 VGA DAC Signals Routing (27)
2.7.3 TMDS / LVDS Transmission Line of the SiS301B Card (27)
2.8 MuTIOL TM Design (29)
2.9 MII Design (30)
2.10 LAN PHY Design (31)
2.10.1 Placement and Trace Routing (32)
2.10.2 Power and Ground Plane (33)
2.11 SiS740 Power Consumption (34)
2.12 Noise Filter for PLL Function (35)
3 DESIGN CHECKLIST (37)
3.1 General Design Checklist (37)
3.2 CLK Bus Routing Checklist (38)
3.3 S2K Bus Design Checklist (40)
3.4 SDRAM Bus Checklist (41)
3.4.1 Pure DDR SDRAM (41)
3.4.2 Pure SDR SDRAM (44)
3.4.3 Mixed SDRAM Layout Guideline (48)
3.5 VGA and V-DIMM Bus Checklist (52)
3.6 MuTIOL TM Bus Checklist (53)
3.7 IDE Bus Checklist (54)
3.8 PCI Bus Checklist (56)
3.9 USB Bus Checklist (57)
3.10 ACR and AC97 Codec Checklist (59)
3.11 MII Signals Checklist (60)
Figure 1-1 SiS740/961 System Block Diagram (5)
Figure 2.1-1 Component Placement and Signal Routing for ATX Form Factor ( with Mixed SDRAM Application) (6)
Figure 2.1-2 Component Placement and Signal Routing for Micro-ATX Form Factor (with Pure DDR SDRAM Application) (7)
Figure 2.2-1 Balls Placement of chip SiS740 (8)
Figure 2.2-2 Signals Placement of Chip SiS961 (9)
Figure 2.3-1 Dimensions for BGA Signals Routing (11)
Figure 2.3-2 Dimensions for BGA Power and Ground Routing (11)
Figure 2.3-3 The Recommendation for BGA Power/Ground Routing (12)
Figure 2.3-4 Example for BGA Layout (13)
Figure 2.3-5 SiS740 Ball Package (15)
Figure 2.3-6 SiS961 Ball Package (16)
Figure 2.4-1 Schematics and Layout for HSTL VREF (20)
Figure 2.7-1 SiS740 GUI Block Diagram (25)
Figure 2.7-2 SiS740 DAC Routing Model (26)
Figure 2.7-3 Schematics Example for VGA Analog Power/Ground (26)
Figure 2.7-4 V-DIMM manufacture (27)
Figure 2.7-5 Example of acceptable differential signal routing (28)
Figure 2.10-1 Schematics for LAN signals (32)
Figure 2.10-2 Layout Recommendation for TPO± and TPI± (33)
Figure 2.10-3 Power/Ground Isolation for Transformer (33)
Figure 2.12-1 Layout Examples for AVDD & AVSS (35)
Figure 2.12-2 Example Circuitries for AVDD and AVSS (36)
Figure 3.1-1 4-Layer PCB Stack-up (37)
Figure 3.4-1 Pure DDR SDRAM Routing (42)
Figure 3.4-2 Pure DDR SDRAM CLK Routing (43)
Figure 3.4-3 Pure SDR SDRAM Routing (46)
Figure 3.4-4 Pure SDR SDRAM CLK Routing (47)
Figure 3.4-5 Mixed SDRAM Signals Layout & Routing T opology (48)
Figure 3.4-6 Mixed SDRAM Clocks Layout & Routing T opology (49)
Figure 3.7-1 T opology of IDE Signals (55)
Figure 3.9-1 T opology of USB Signals (57)
Figure 3.11-1 T opology of MII Signals (60)
T able 2.3-1 Hardware Trap of SiS740 System (13)
T able 2.3-2 Reference plane of SiS740 Signal (14)
T able 2.4-1 Recommendations for Board Design (17)
T able 2.4-2 K7 System Bus Signal Groups and Corresponding Forward Clocks (17)
T able 2.4-3 K7 System Bus Signal Reference Plane in SiS740 Demoboard (17)
T able 2.4-4 K7 System Bus Signals that Synchronize with CPUCLK and CPUCLK# (19)
T able 2.4-5 Other K7 Signals Layout Guidelines (19)
T able 2.4-6 Core Frequency Hardware Trap Configuration (21)
T able 2.5-1 Mixed Pins List for SiS740 (22)
T able 2.6-1 Clock Requirements for Clock Generator (24)
T able 2.8-1 MuTIOL TM Connect Interface (29)
T able 2.8-2 Special Signals for MuTIOL TM (29)
T able 2.10-1 TP Transformer Specification (31)
T able 2.10-2 TP Transformer Sources (31)
T able 2.10-3 Crystal Specifications (32)
T able 2.11-1 SiS740 Power Consumption (34)
T able 2.11-2 Recommended Trace Width for Power Signals (34)
T able 3.4-1 Pure DDR SDRAM Signals Grouping (41)
T able 3.4-2 Pure DDR SDRAM Trace Length Recommendations (41)
T able 3.4-3 Pure SDR SDRAM Signals Grouping (44)
T able 3.4-4 Pure SDR SDRAM Trace Length Recommendations (45)
T able 3.4-5 Mixed SDRAM Signals Grouping (50)
T able 3.4-6 Mixed SDRAM Trace Length Recommendations (50)
1 Introduction
The new SiS chipsets, SiS740, integrated 3D graphic provides a high performance and low cost Desktop solution for the AMD Socket A series CPUs by integrating a high performance North Bridge, advanced hardware 2D/3D GUI engine. SiS740 support 3-DIMM with Double Data Rate (DDR) SDRAM up to 266MHz, or with traditional SDRAM bandwidth up to 133MHz and also support 266MHz up to 533MB/s speed Link Connect interface to Sound bridge SiS961. By integrating the Ultra-AGPII TM technology, advanced 256-bit 3D engine and graphic display interface which adopts Share System Memory Architecture that can flexibly utilize the system memory up to 128MB, SiS740 GUI engine delivers equal to AGP 8X performance, up to 2 GB/s memory bandwidth. Furthermore, SiS740 provides powerful hardware decoding DVD accelerator to improve the DVD playback performance.
This document provides valuable references and design guidelines for developing SiS740 system. The North-Bridge SiS740 can support AMD Polemino, Athlon, and Duron processors and SDR, DDR, Mixed SDRAM. SiS740 also support AMD PowerNow! dynamic power management technique. And the most important part of SiS740 system is that it includes hardware 2D/3D GUI engine and support dual monitors with SiS301B. Users can use the integrated GUI to the monitor and add the SiS301B card to connect the secondary monitor, LCD, no more use any AGP card.
The South Bridge SiS961 support the functions of up to six PCI slots, six USB connects, Ultra-DMA100 IDE, AC’ 97-link, 3D audio, MII/GPSI interface, ACPI, KBC, RTC and LPC.
The Full System Block Diagram SiS740 and SiS961 are illustrated as below:
Figure 1-1 SiS740/961 System Block Diagram
2 Motherboard Consideration
2.1 Placement Design
The component placement examples of SiS740/961 Demo Board describing the recommended placements and signal routing on a ATX motherboard with mixed SDRAM and Micro-ATX motherboard with DDR SDRAM are illustrated as following figures:
Figure 2.1-1 Component Placement and Signal Routing for ATX Form Factor
( with Mixed SDRAM Application)
For Micro - A TX motherboard, the component placement with Pure DDR and Pure SDR SDRAM can design similar as following figure:
Figure 2.1-2 Component Placement and Signal Routing for Micro-ATX Form Factor
(with Pure DDR SDRAM Application)
2.2 SiS Chipset Design
To route all signals in a four-layer motherboard, not only the pin assignment in SiS740 was able to minimize the crossover between different kinds of signals, but also the signal arrangement in SiS740 followed the bus orders.
On the basis of the ATX form factor, the SiS740 signal arrangements are illustrated in Figure 2.2-1.
Figure 2.2-1 Balls Placement of chip SiS740
And the SiS961 signal arrangements are illustrated in Figure 2.2-2.
Figure 2.2-2 Signals Placement of Chip SiS961
2.3 BGA Component Layout Guideline
The chip SiS740 package is 539-Balls BGA and SiS961 package is 371-Balls BGA. And they are maximum 5 rows of balls arranged along the edge of SiS740/961 package. To achieve a 4-layer motherboard, some routing techniques are required and narrated in the following text. As following the layout rules of the old SiS chips that have maximum 6 rows of balls arranged along the edge, the rules can define and observe more elasticized by layout case. As general case, the signals on the outer 3 rows can be routed on the component side and the signals on the inner 3 rows can be routed on the solder side by through hole. Therefore, it is necessary to put two traces between two nearby pads. The suggested dimensions are listed below and drawn in Figure 2.3-1 ~ Figure 2.3-4.
Traces for Signals:
Trace Width: 5 mils
Trace Space: 5 mils
Pads for Signals:
Pad Diameter: 20 mils
Vias for Signals:
Via Pad Diameter: 24 mils
Via Hole Diameter: 12 mils
Trace for Power and Ground:
Trace Width: at lease 12 mils
Pads for Power and Ground:
Pad Diameter: 24 mils
Vias for Power and Ground:
Via Pad Diameter: 28 mils
Via Hole Diameter: 16 mils
Note: All the Vias must be covered by solder mask. And the center distance of two nearby balls is 50 mils.
Figure 2.3-1 Dimensions for BGA Signals Routing
Figure 2.3-2 Dimensions for BGA Power and Ground Routing
To reduce the power/ground bounce issue, SiS recommends that the power/ground layer reserve the channel, additionally, the number of Vias to power/ground should be not less than that in Figure 2.3-3.
Figure 2.3-3 The Recommendation for BGA Power/Ground Routing
When arrange the vias to signal/power/ground should consider the reserved channel for the current return path
on power/ground layer, as shown in Figure 2.3-4.
The hardware Trap of SiS740 and SiS961 are list as below
Table 2.3-1 Hardware Trap of SiS740 System
Symbol Description
DLLENN CPUCLK SDCLK ZCLK PLL/DLL Circuit Enable 1: Disable
0: Enable
DRAM_SEL DDR/SDR SDRAM Selection 1: DDR SDRAM
0: SDR SDRAM
TRAP[3:0] CPU Clock Divider
TRAP[3:0] Ratio TRAP[3:0]
Ratio 0000 11.0
1000
7.0 0001 11.5
1001
7.5 0010 12.0
1010
8.0 0011 12.5
1011
8.5 0100 5.0
1100
9.0 0101 5.5
1101
9.5 0110 6.0
1110
10.0 0111 6.5
1111
10.5
TESTMODE[1:0] System Clock Speed 00: 100MHz
01: 66MHz
10: 90MHz
11: 133MHz
TESTMODE2 740 Debug Mode 1: Enable
0: Disable
RSYNC VGA Interrupt function 1: Enable
0: Disable
LSYNC Panel Link Enable 1: Enable
0: Disable
CSYNC Video Bridge Enable 1: Enable
0: Disable
VBCTL0 PAL/NTSC Selection 1: PAL
0: NTSC
VBCTL1 ZCLK PLL/DLL Enable 1: Disable
0: Enable
For routing of the signals in subtract layer, the inner row balls of the SiS740 chip must be reference to Powers. When routing the signal of chip SiS740 in the soldier side of the 4-layer motherboard, SiS recommends to put GND plane in the second layer and Power plane in the third layer to continue reference power plane from subtract layer to Main-board. For routing to avoid the critical signals cross over the different power planes issue, the signals of SiS 740 chip referenced to Power in the chipset subtract list as the Table. And the high light signal are the critical signal.
Table 2.3-2 Reference plane of SiS740 Signal
Name Ball
Group Name Ball
Group Name Ball
Group SDATA1# E19 S2K SDATA51# J23 S2K CLKFWDRST E12 S2K SDATA8# E17 S2K SDATA52# L22 S2K HSTLVREFA M22 S2K SDATA10# D17 S2K SDATA61# J22 S2K DDC2DATA E5 VB SDATA12# E18 S2K SADDIN7# D13 S2K TESTMODE1 E7 TRAP SDATA15# D19 S2K SADDIN8# E13 S2K DRAM_SEL R5 TRAP SDATA26# E21 S2K SADDOUT4# P23 S2K ENTEST F5 TRAP SDATA27# E20 S2K SADDOUT10# R23 S2K VDDREFA N22 SDRAM SDATA28# D21 S2K SADDOUT11# P22 S2K PWROK T5 OTHER SDATA29# D22 S2K HSTLVREFA M22 S2K TRAP2 E8 TRAP SDATA34# E22 S2K S2KCOMPPD T22 S2K VBCAD G5 VB SDATA37# G22 S2K S2KCOMPND R22 S2K VBD2 H5 VB SDATA46# F22 S2K Z1XAVDD R4 MuTIOL VCOMP D9 VB SDATA48# H22 S2K Z4XAVDD T4 MuTIOL VRSET E10 VB SDATA50# K22 S2K VDDZCMP P5 MuTIOL
And the SiS740 with 539 balls (35X35 mm) package drawing and dimensions is illustrated in Figure 2.3-5.
Figure 2.3-5 SiS740 Ball Package
The SiS961 with 371 balls (27X27 mm) package drawing and dimensions is illustrated in Figure 2.3-6.
Figure 2.3-5 SiS740 Ball Package
Figure 2.3-6 SiS961 Ball Package
2.4 AMD Socket A CPU Design
The summary of layout for SiS740 and routing guidelines for HSTL:
1. Route most of the HSTL signal lines on the inner layers if use the 6-layer board.
2. The trace length of HSTL should be less than 5.0 inches.
3. The characteristic impedance of transmission lines on board is within the range of 60? ±20%.
4. The dielectric constant of substrate should be 4.2 to 4.8.
5. Maintain the signals referred to VSS/VCC_CORE are routed on the layer referred to VSS/VCC_CORE
and keep the reference plane in their integrity.
Table 2.4-1 Recommendations for Board Design
PARAMETER VALUE UNITS
Socket A to SiS740 trace length 5.0 Inches Signal trace impedance 48~72 ? Signal trace width 5 Mils Signal trace spacing 10 Mils Substrate thickness 5 Mils Substrate dielectric constant 4.5 ± 0.3
Signal propagation velocity 1.8~2.0
ns/ft
For classes of rule, we divide the HSTL signals to six groups that correlate to their corresponding forward clocks and the signals that synchronize with system clocks in Table 2.4-2. In the SS50 demo-board, the layout references plane and layout guidelines of each signal are illustrated in Table 2.4-3. The layout guidelines of other K7 signals are listed in Table 2.4-4,2.4-5.
Table 2.4-2 K7 System Bus Signal Groups and Corresponding Forward Clocks SIGNAL GROUPS CLOCKS A. SDATA[15:0]# SDATAOUTCLK[0]#, SDATAINCLK[0]# B. SDATA[31:16]# SDATAOUTCLK[1]#, SDATAINCLK[1]# C. SDATA[47:32]# SDATAOUTCLK[2]#, SDATAINCLK[2]# D. SDATA[63:48]# SDATAOUTCLK[3]#, SDATAINCLK[3]# E. SADDOUT[14:2]#
SADDOUTCLK#
F. SADDIN#[14:2], SDATAINVAL#
SADDINCLK#
In each group, the mismatch of all DATA trace lengths within +/-50 mils, and the SDATAOUTCLK#[3:0] length is the same to minimum length. Because of the AMD requirement LCL circuits added to SDATAINCLK#[3:0] signals, all SDATAINCLK#[3:0] must short than SADDINCLK#[3:0] 1.5 inch as possible.
Table 2.4-3 K7 System Bus Signal Reference Plane in SiS740 SS50 Demo-board GROUP SIGNAL NAME REF. GROUP SIGNAL NAME REF. SADDIN#2 GROUND SADDOUT#2 GROUND SADDIN#3 GROUND SADDOUT#3 GROUND SADDIN#4 GROUND SADDOUT#4 VCC_CORE SADDIN#5 GROUND SADDOUT#5 GROUND SADDIN#6 VCC_CORE SADDOUT#6 GROUND SADDIN#7 VCC_CORE SADDOUT#7 GROUND SADDIN
SADDIN#8
VCC_CORE
SADDOUT
SADDOUT#8
GROUND
SADDIN#9 GROUND SADDOUT#9 GROUND SADDIN#10 GROUND SADDOUT#10 VCC_CORE SADDIN#11 GROUND SADDOUT#11 VCC_CORE SADDIN#12 GROUND SADDOUT#12 GROUND SADDIN#13 GROUND SADDOUT#13 GROUND SADDIN#14 GROUND SADDOUT#14 GROUND SADDINCLK# GROUND SADDOUTCLK#
GROUND
SDATAINVAL# VCC_CORE
SDATA#0 GROUND SDATA#16 GROUND SDATA#1 VCC_CORE SDATA#17 GROUND SDATA#2 GROUND SDATA#18 GROUND SDATA#3 GROUND SDATA#19 GROUND SDATA#4 GROUND SDATA#20 GROUND SDATA#5 GROUND SDATA#21 GROUND SDATA#6 GROUND SDATA#22 GROUND SDATA#7
GROUND SDATA#23 GROUND SDATA#8 VCC_CORE SDATA#24 VCC_CORE SDATA#9 GROUND SDATA#25 VCC_CORE SDATA#10 VCC_CORE SDATA#26 VCC_CORE SDATA#11 GROUND SDATA#27 VCC_CORE SDATA#12 VCC_CORE SDATA#28 VCC_CORE SDATA#13 GROUND SDATA#29 VCC_CORE SDATA#14 GROUND SDATA#30 VCC_CORE SDATA#15 VCC_CORE SDATA#31 VCC_CORE SDATAINCLK#0 GROUND SDATAINCLK#1 GROUND SDATA0
SDATAOUTCLK#0
VCC_CORE SDATA1
SDATAOUTCLK#1
GROUND SDATA#32 VCC_CORE SDATA#48 VCC_CORE SDATA#33 VCC_CORE SDATA#49 GROUND SDATA#34 VCC_CORE SDATA#50 VCC_CORE SDATA#35 VCC_CORE SDATA#51 VCC_CORE SDATA#36 VCC_CORE SDATA#52 VCC_CORE SDATA#37 VCC_CORE SDATA#53 GROUND SDATA#38 GROUND SDATA#54 VCC_CORE SDATA#39
GROUND SDATA#55 VCC_CORE SDATA#40 GROUND SDATA#56 GROUND SDATA#41 GROUND SDATA#57 GROUND SDATA#42 GROUND SDATA#58 GROUND SDATA#43 GROUND SDATA#59 GROUND SDATA#44 GROUND SDATA#60 GROUND SDATA#45 GROUND SDATA#61 VCC_CORE SDATA#46 VCC_CORE SDATA#62 GROUND SDATA#47 GROUND SDATA#63 GROUND SDATAINCLK#2 GROUND SDATAINCLK#3 GROUND SDATA2
SDATAOUTCLK#2
VCC_CORE
SDATA3 SDATAOUTCLK#3
GROUND
Table 2.4-4 K7 System Bus Signals that Synchronize with CPUCLK and CPUCLK#
SIGNAL NAME
CLOCKS
CLKFWDRST CONNECT PROCRDY CPUCLK and CPUCLK#
CLKFWDRST VCC_CORE
CONNECT VCC_CORE SCLK
PROCRDY VCC_CORE
Route as short as possible, and no greater than 5
inch .
Table 2.4-5 Other K7 Signals Layout Guidelines
SIGNAL NAME
LAYOUT GUIDELINES
CPUCLK, CPUCLK#
1.Route as differential pair ( 5/5/5 trace/space/trace ) with 50 ohm target impedance
2.Match lengths to within +/-50 mils
3.Maintain 20 mil clearance to other signals
4.Maintain 50 mil clearance to self
PICD[1:0], PICCLK FERR#
NMI, INTR, SMI#, INIT#, A20M#, IGNNE#, STPCLK#, RESET# FID[3:0] PWROK VCC2SEL VID[3:0]
Route as short as possible COREFB+, COREFB- Route as differential pair with 15 mil width
Suggested Low-pass Filter Implementations for INCLKs
To remove the crosstalk coupled from switching data bus, the L-C-L FILTER is recommended to add on the INCLK traces. All of SDATAINCLK#[3:0] and SADDINCLK# traces should be applied to such a circuit.
Beside the rules published before, additional rules should be followed either:
1. L-C-L FILTER will suffer ~300ps hold timing. Do shorten ~1.5 inches of INCLK traces to maintain the same timing as usual.
2. L-C-L FILTER must be placed at the center of the InClk trace or close to 740.
3. High-Q discrete components must be used to prevent signal losing.
4. Don’t route any trace within 20mils of the inductors for mutual inductance coupling concerning.