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verilog电子时钟代码

//clk:秒功能的时钟信号,为1Hz的脉冲信号
//time_set_en:时间设置使能信号
//time_clear(键8):时钟显示的清零
//hourh_set,hourl_set,minh_set,minl_set,sech_set,secl_set:设置后的小时、分、秒
//hourh,hourl:小时的高低位
//minh,minl:分的高低位
//sech,secl:秒的高低位
//cout:进位输出,即计满24小时,向天产生的进位输出信号
module time_count(clk,time_set_en,time_clear,hourh_set,hourl_set,minh_set,minl_set,sech_set,secl_set,hourh,hourl,minh,minl,sech,secl,cout);
input clk;
input time_set_en,time_clear;
input[3:0]hourh_set,hourl_set,minh_set,minl_set,sech_set,secl_set;
output[3:0]hourh,hourl,minh,minl,sech,secl;
output cout;
reg[3:0]hourh,hourl,minh,minl,sech,secl;
reg cout;
reg c1,c2; //c1和c2分别为秒向分,分向时的进位

always@(posedge time_clear)
begin
hourh<=0;
hourl<=0;
minh<=0;
minl<=0;
sech<=0;
secl<=0;
end
always@(posedge time_set_en or posedge clk )
begin
if(time_set_en)
begin
sech<=sech_set;
secl<=secl_set;
end

else
begin
if(secl==9)
begin
secl<=0;
if(sech==5)
begin
sech<=0;
c1<=1;
end
else
begin
sech<=sech+1;
end
end
else
begin
secl<=secl+1;
c1<=0;
end
end
end

always@(posedge c1 or posedge time_set_en)
begin
if(time_set_en)
begin
minh<=minh_set;
minl<=minl_set;
end
else if(minl==9)
begin
minl<=0;
if(minh==5)
begin
minh<=0;
c2<=1;
end
else
begin
minh<=minh+1;
end
end
else
begin
minl<=minl+1;
c2<=0;
end
end

always@(posedge c2 or posedge time_set_en)
begin
if(time_set_en)
begin
hourh<=hourh_set;
hourl<=hourl_set;
end
else if((hourh==2)&&(hourl==3))
begin
hourh<=0;
hourl<=0;
cout<=1;
end
else if(hourl==9)
begin
hourl<=0;
if(hourh==2)
hourh<=0;
else
hourh<=hourh+1;
end
else
begin
hourl<=hourl+1;
cout<=0;
end
end
endmodule

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