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FEATURES APPLICATIONS
DESCRIPTION
TVP7000
SLES143–SEPTEMBER2005
TRIPLE8/10-BIT,150/110MSPS,VIDEO
AND GRAPHICS DIGITIZER WITH ANALOG PLL
?LCD TV/Monitors/Projectors
?Analog Channels
?DLP TV/Projectors
–-6dB to6dB Analog Gain
?PDP TV/Monitors
–Analog Input MUXs
?PCTV Set-Top Boxes
–Auto Video Clamp
?Digital Image Processing –Three Digitizing Channels,Each With
?Video Capture/Video Editing Independently Controllable Clamp,PGA,
?Scan Rate/Image Resolution Converters and ADC
?Video Conferencing
–Clamping:Selectable Clamping Between
?Video/Graphics Digitizing Equipment Bottom Level and Mid-level
–Offset:1024-Step Programmable RGB or
YPbPr Offset Control
TVP7000is a complete solution for digitizing video –PGA:8-Bit Programmable Gain Amplifier
and graphic signals in RGB or YPbPr color spaces.
–ADC:8/10-Bit150/110MSPS A/D Converter
The device supports pixel rates up to150MHz.
–Automatic Level Control Circuit Therefore,it can be used for PC graphics digitizing
up to the VESA standard of SXGA(1280×1024)–Composite Sync:Integrated Sync-on-Green
resolution at75Hz screen refresh rate,and in video Extraction From GreenLuminance Channel
environments for the digitizing of digital TV formats,–Support for DC and AC-Coupled Input
including HDTV up https://www.doczj.com/doc/6912804693.html,P7000can be used Signals to digitize CVBS and S-Video signal with10-bit
?PLL ADCs.
–Fully Integrated Analog PLL for Pixel Clock The TVP7000is powered from 3.3-V and 1.8-V
Generation supply and integrates a triple high-performance A/D
converter with clamping functions and variable gain,–12-150MHz Pixel Clock Generation From
independently programmable for each channel.The HSYNC Input
clamping timing window is provided by an external –Adjustable PLL Loop Bandwidth for
pulse or can be generated internally.The TVP7000 Minimum Jitter includes analog slicing circuitry on the Y or G input to
–5-Bit Programmable Subpixel Accurate support sync-on-luminance or sync-on-green extrac-Positioning of Sampling Phase tion.In addition,TVP7000can extract discrete
HSYNC and VSYNC from composite sync using a ?Output Formatter
sync slicer.
–Support for RGB/YCbCr4:4:4and YCbCr
TVP7000also contains a complete analog PLL block 4:2:2Output Modes to Reduce Board Traces
to generate a pixel clock from the HSYNC input.Pixel –Dedicated DATACLK Output for Easy
clock output frequencies range from12MHz to150 Latching of Output Data
MHz.
?System
All programming of the part is done via an indus-–Industry-Standard Normal/Fast I2C Interface try-standard I2C interface,which supports both read-With Register Readback Capability ing and writing of register settings.The TVP7000is –Space-Saving TQFP-100Pin Package available in a space-saving TQFP100-pin PowerPAD
package.
–Thermally-Enhanced PowerPAD?Package
for Better Heat Dissipation
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.Copyright?2005,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas
Instruments standard warranty.Production processing does not
necessarily include testing of all parameters.
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ROUT[9:0]
GOUT[9:0]
RIN_1SCL SDA I2CA
GIN_1BIN_1HSYNC_A VSYNC_A COAST CLAMP FILT1SOGIN_1RESETB
PWDN BOUT[9:0]
SOGOUT HSOUT VSOUT
DATACLK RIN_2GIN_2BIN_2SOGIN_2HSYNC_B VSYNC_B FILT2RIN_3GIN_3GIN_4SOGIN_3BIN_3
TVP7000
SLES143–SEPTEMBER 2005
ORDERING INFORMATION
PACKAGED DEVICES
T A 100-PIN PLASTIC FLATPACK PowerPAD?
0°C to 70°C
TVP7000PZP
FUNCTIONAL BLOCK DIAGRAM
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TERMINAL ASSIGNMENTS
TVP7000
100?Pin TQFP Package
(Top View)
SOGIN_1GIN_1A18GND A18VDD A18GND A18VDD A18VDD A18GND RIN_3RIN_2RIN_1A33GND A33VDD A33VDD A33GND BIN_3BIN_2BIN_1A18VDD A18GND NSUB TEST VSOUT HSOUT SOGOUT
I O V D D I O G N D D A T A C L K B _9B _8B _7B _6B _5B _4B _3B _2B _1B _0D V D D G N D I O V D D I O G N D G _9G _8G _7G _6G _5G _4G _3G _2SDA
SCL I2CA TMS RESETB PWDN DVDD GND IOGND IOVDD R_0R_1R_2R_3R_4IOGND R_5R_6R_7R_8R_9IOGND IOVDD G_0G_1
G I N _2S O G I N _2G I N _3S O G I N _3G I N _4A 33G N D A 33V D D A 33V D D A 33G N D N S U B P L L _A 18G N D P L L _F F I L T 2F I L T 1P L L _A 18G N D P L L _A 18V D D P L L _A 18V D D P L L _A 18G N D H S Y N C _B H S Y N C _A E X T _C L K V S Y N C _B V S Y N C _A C O A S T C L A M P
12345678910111213141516171819202122232425
75747372717069686766656463626160595857565554535251
100999897969594939291908988878685848382818079787776
26272829303132333435363738394041424344454647484950
TVP7000
SLES143–SEPTEMBER 2005
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TVP7000
SLES143–SEPTEMBER 2005
TERMINAL FUNCTIONS
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ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS
TVP7000 SLES143–SEPTEMBER2005
TERMINAL FUNCTIONS(continued)
TERMINAL
I/O DESCRIPTION
NAME NO.
VSYNC_A78I Vertical sync input A
VSYNC_B79I Vertical sync input B.Unused inputs can be connected to ground.
HSYNC_A81I Horizontal Sync input A
HSYNC_B82I Horizontal Sync input B.Unused inputs can be connected to ground.
SOGIN11I Sync-on-green input1
SOGIN299I Sync-on-green input2
SOGIN397i Sync-on-green input3.Unused inputs should be connected to ground using a10nF capacitor. VSOUT23O Vertical sync output
HSOUT24O Horizontal sync output
SOGOUT25O Sync-on-green slicer output
over operating free-air temperature range(unless otherwise noted)(1)
UNIT
IOVDD to IOGND–0.5V to4.5V
DVDD to GND–0.5V to2.3V Supply voltage range
PLL_A18VDD to PLL_A18GND and A18VDD to A18GND–0.5V to2.3V
A33VDD to A33GND–0.5V to4.5V Digital input voltage range VI to GND–0.5V to4.5V
Analog input voltage range AI to A33GND–0.2V to2.3V
Digital output voltage range VO to GND–0.5V to4.5V
TA Operating free-air temperature0°C to70°C
Tstg Storage temperature–65°C to150°C
(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
over operating free-air temperature range,T
A
=0°C to70°C(unless otherwise noted)
MIN NOM MAX UNIT IOVDD Digital I/O supply voltage 3.0 3.3 3.6V DVDD Digital supply voltage 1.70 1.8 1.9V
PLL_A18VDD Analog PLL supply voltage 1.70 1.8 1.9V
A18VDD Analog supply voltage 1.70 1.8 1.9V
A33VDD Analog supply voltage 3.0 3.3 3.6V
V I(P–P)Analog input voltage(ac–coupling necessary)0.5 2.0V
V IH Digital input voltage high0.7IOVDD V
V IL Digital input voltage low0.3IOVDD V
I OH High–level output current2mA
I OL Low–level output current–2mA
I OH_DATACLK DATACLK high–level output current4mA
I OL_DATACLK DATACLK low–level output current–4mA
T A Operating free–air temperature070°C
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ELECTRICAL CHARACTERISTICS
TVP7000
SLES143–SEPTEMBER 2005
IOVDD =3.3V,DVDD =1.8V,PLL_A18VDD =1.8V,A18VDD =1.8V,A33VDD =3.3V,T A =25°C
PARAMETER
TEST CONDITIONS
MIN TYP (1)
MAX (2)
UNIT
POWER SUPPLY I IOVDDD 3.3-V supply current 78.75MHz 80130mA I DVDD 1.8-V supply current
78.75MHz 253260mA P TOT Total power dissipation,normal mode 78.75MHz 719897mW I IOVDDD 3.3-V supply current 108MHz 101160mA I DVDD 1.8-V supply current
108MHz 261275mA P TOT Total power dissipation,normal mode 108MHz 8031023mW I IOVDDD 3.3-V supply current 148.5MHz 128240mA I DVDD 1.8-V supply current
148.5MHz 250280mA P TOT Total power dissipation,normal mode 148.5MHz
8721296
mW P DOWN Total power dissipation,power–down mode
1
mW
(1)SMPTE color bar RGB input pattern used.
(2)
Worst case vertical line RGB input pattern used.
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ELECTRICAL CHARACTERISTICS
TVP7000 SLES143–SEPTEMBER2005
IOVDD=3.3V,DVDD=1.8V±0.1,PLL_A18VDD=1.8V±0.1,A18VDD=1.8V±0.1,A33VDD=3.3V,T
A =0°C to70°C
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INTERFACE
Input voltage range By design0.5 1.0 2.0Vpp
Z I Input impedance,analog video inputs By design500k?DIGITAL LOGIC INTERFACE
C i Input capacitance By design10pF
Z i Input impedance By design500k?
V OH Output voltage high I OH=2mA0.8IOVDD V
V OL Output voltage low I OL=–2mA0.2IOVDD V
V OH_SCLK DATACLK output voltage high I OH=4mA0.8IOVDD V
V OL_SCLK DATACLK output voltage low I OH=–2mA0.2IOVDD V
V IH High-level input voltage By design0.7IOVDD V
V IL Low-level input voltage By design0.3IOVDD V
A/D CONVERTERS
Conversion rate12150MSPS
10bit,110MHz-1±0.5+1
DNL DC differential nonlinearity LSB
8bit,150MHz-1±0.5+1
10bit,110MHz-4±1+4
INL DC integral nonlinearity LSB
8bit,150MHz-4±1+4 Missing code8bit,150MHz none
SNR Signal-to-noise ratio10MHz,1.0V P–P at11052dB
MSPS
Analog bandwidth By design500MHz PLL
Clock jitter500ps
Phase adjustment11.6degree
VCO frequency range12150MHz
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TIMING REQUIREMENTS
DATACLK
R, R, B, HSOUT TVP7000
SLES143–SEPTEMBER 2005
PARAMETER
TEST CONDITIONS (1)
MIN
TYP
MAX
UNIT
CLOCKS,VIDEO DATA,SYNC TIMING
Duty cycle DATACLK
50%t 1DATACLK rise time 10%to 90%1ns t 2DATACLK fall time 90%to 10%
1
ns t 3Output delay time
1.5
3.5
ns
(1)
Measured with a load of 15pF.
Figure 1.Clock,Video Data,and Sync Timing
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TIMING REQUIREMENTS
TVP7000 SLES143–SEPTEMBER2005
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I2C HOST PORT TIMING
t1Bus free time between STOP and START Specified by design 1.3μs
t2Setup time for a(repeated)START condition Specified by design0.6μs
t3Hold time(repeated)START condition Specified by design0.6μs
t4Setup time for a STOP condition Specified by design0.6ns
t5Data setup time Specified by design100ns
t6Data hold time Specified by design00.9μs
t7Rise time SDA and SCL signal Specified by design250ns
t8Fall time SDA and SCL signal Specified by design250ns
C b Capacitive load for each bus line Specified by design400pF
f12C I2C clock frequency Specified by design400kHz
Figure2.I2C Host Port Timing
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FUNCTIONAL DESCRIPTION
Analog Channel
TVP7000
SLES143–SEPTEMBER 2005
The TVP7000contains three identical analog channels that are independently programmable.Each channel consists of a clamping circuit,a programmable gain amplifier,automatic offset control and an A/D converter.Analog Input Switch Control
TVP7000has 3analog channels that accept up to 10video inputs.The user can configure the internal analog video switches via the I2C interface.The 10analog video inputs can be used for different input configurations some of which are:
?Up to 10selectable individual composite video inputs ?Up to 2selectable RGB graphics inputs
?Up to 3selectable YPbPr video HD/SD inputs
The input selection is performed by the input select register at I 2C subaddress 0×19and 0×1A (see Input Mux Select 1and Input Mux Select 2)Analog Input Clamping
An internal clamping circuit restores the AC-coupled video/graphic signal to a fixed DC level.The clamping circuit provides line-by-line restoration of the signal black level to a fixed DC reference voltage.The selection between bottom and mid level clamping is performed by I 2C subaddress 0×10(see Sync On_Green Threshold)
The internal clamping time can be adjusted by I 2C clamp start and width registers at subaddress 0×05and 0×06(see Clamp Start and Clamp Width)Programmable Gain Amplifier (PGA)
The TVP7000PGA can scale a signal with a voltage-input compliance of 0.5-Vpp to 2-Vpp to a full-scale 10-bit A/D output code range.A 4-bit code sets the coarse gain (Red Coarse Gain,Green Coarse Gain,Blue Coarse Gain)with individual adjustment per channel.Minimum gain corresponds to a code 0×0(2-Vpp full-scale input,–6dB gain)while maximum gain corresponds to code 0×F (0.5-Vpp full-scale,+6dB gain).TVP7000also has 8-bit fine gain control (Red Fine Gain,Green Fine Gain,Blue Fine Gain)for RGB independently ranging from 1to 2.For a normal PC graphics input,the fine gain will be used mostly.Programmable Offset Control and Automatic Level Control (ALC)
The TVP7000supports a programmable offset control for RGB independently.A 6-bit code sets the coarse offset (Red Coarse Offset,Green Coarse Offset,Blue Coarse Offset)with individual adjustment per channel.The coarse offset ranges from –32LSB to +31LSB.The coarse offset registers apply before the ADC.A 10-bit fine offset registers (Red Fine Offset,Green Fine Offset,Blue Fine Offset)apply after the ADC.The fine offset ranges from –512LSB to +511LSB.
ALC circuit maintains the level of the signal to be set at a value which is programmed at fine offset I 2C register.It consists of pixel averaging filter and feedback loop.This ALC function can be enabled or disabled by I 2C register address at 0×26.ALC circuit needs a timing pulse generated internally but user should program the position properly.The ALC pulse must be positioning after the clamp pulse.The position of ALC pulse is controlled by ALC placement I 2C register at address 0×31.This is available only for internal ALC pulse timing.For external clamp,the timing control of clamp is not applicable so the ALC pulse control is also not applicable.Therefore it is suggested to keep the external clamp pulse as long as possible.ALC is applied as same position of external clamp pulse.A/D Converters
All ADCs have a resolution of 10-bits and can operate up to 150MSPS.All A/D channels receive an identical clock from the on-chip phase-locked loop (PLL)at a frequency between 12MHz and 150MHz.All ADC reference voltages are generated internally.Also the external sampling clock can be used.
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COAST HSYNC
PLL Control
Register 0x03
Bit [5:3]
PLL Control
Register 0x03
Bit [7:6]
Phase Select
Register 0x04
Bit [7:3]
ADC
Sampling
CLK
PLL Divide
Register 0x01
and 0x02
Bit [11:0]
TVP7000
SLES143–SEPTEMBER2005
Analog PLL
The analog PLL generates a high-frequency internal clock used by the ADC sampling and data clocking out to derive the pixel output frequency with programmable phase.The reference signal for this PLL is the horizontal sync signal supplied on the HSYNC input or from extracted horizontal sync of sync slicer block for embedded sync signals.The analog PLL consisted of phase detector,loop filter,voltage controlled oscillator(VCO),divider and phase select.The analog block diagram is shown at Figure3.
Figure3.PLL Block Diagram
The COAST signal is used to allow the PLL to keep running at the same frequency,in the absence of the incoming HSYNC signal or disordered HSYNC period.This is useful during the vertical sync period,or any other time that the HSYNC is not available.
There are several PLL controls to produce the correct sampling clock.The12-bit divider register is programmable to select exact multiplication number to generate the pixel clock in the range of12MHz to150 MHz.The3-bit loop filter current control register is to control the charge pump current that drives the low-pass loop filter.The applicable current values are listed in the Table1.
The2-bit VCO range control is to improve the noise performance of the TVP7000.The frequency ranges for the VCO are shown in Table1.The phase of the PLL generated clock can be programmed in32uniform steps over a single clock degrees phase resolution)so that the sampling phase of the ADC can be accurately controlled.
In addition to sourcing the ADC channel clock from the PLL,an external pixel clock can be used(from pin80). The PLL characteristics are determined by the loop filter design,by the PLL charge pump current,and by the VCO range setting.The loop filter design is shown in Figure4.Supported settings of VCO range and charge pump current for VESA standard display modes are listed in Table1.
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1.5 k?
TVP7000
SLES143–SEPTEMBER2005
Figure4.PLL Loop Filter
Table1.Recommended VCO Range and Charge Pump Current Settings for Supporting Standard Display
Formats
STANDARD RESOL-REFRESH HORIZON-PIXEL RATE PLL Divider PLLDIV PLLDIV LSB Reg03h Output Div-VCO CP CUR-UTION RATE TAL(MHz)Total MSB Reg Reg02h ider Reg RANGE Reg RENT Reg
FRE-pix/line01h[11:4]04h[0]03h[7:6]03h[5:3]
QUENCY
(kHz)
VGA640×48060Hz31.525.1751600(2×)64h00h68h1Low(01b)101b 72Hz37.931.51664(2×)68h00h58h1Low(01b)011b
75Hz37.531.51680(2×)69h00h58h1Low(01b)011b
85Hz43.33683234h00h68h0Low(01b)101b SVGA800×60056Hz35.136102440h00h68h0Low(01b)101b 60Hz37.940105642h00h68h0Low(01b)101b
72Hz48.150104041h00h68h0Low(01b)101b
75Hz46.949.5105642h00h68h0Low(01b)101b
85Hz53.756.25104841h80h68h0Low(01b)101b XGA1024×76860Hz48.465134454h00h58h0Low(01b)011b 70Hz56.575132853h00h A8h0Med(10b)101b
75Hz6078.75131252h00h A8h0Med(10b)101b
85Hz68.794.5137656h00h A8h0Med(10b)101b SXGA1280×102460Hz64108168869h80h A8h0Med(10b)101b 75Hz80135168869h80h98h0Med(10b)011b Video720×480p60Hz31.468271716(2×)6Bh40h68h1Low(01b)101b 720×576p50Hz31.25271728(2×)6Ch00h68h1Low(01b)101b
1280×720p60Hz4574.25165067h20h A8h0Med(10b)101b
1280×720p50Hz37.574.2519807Bh C0h A8h0Med(10b)101b
1920×1080i60Hz33.7574.25220089h80h A8h0Med(10b)101b
1920×1080i50Hz28.12574.252640A5h00h A8h0Med(10b)101b 1920×60Hz67.5148.5220089h80h D8h0High(11b)011b
1080p
1920×50Hz56.25148.52640A5h00h D8h0High(11b)011b
1080p
Sync Slicer
TVP7000includes a circuit that compares the input signal on Green channel to a level150mV(typical value) above the clamped level(sync tip).The slicing level is programmable by I2C register subaddress at0x10.The digital output of the composite sync slicer is available on the SOGOUT pin.
Sync Separator
The sync separator automatically extracts VSYNC and HSYNC from the sliced composite sync input supplied at the SOG input.The G or Y input containing the composite sync must be AC coupled to the SOG input pin using a10-nF capacitor.Support for PC graphics,SDTV,and HDTV up to1080p is provided.
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DATACLK SOGOUT
VSOUT
HSOUT
Timing
TVP7000
SLES143–SEPTEMBER 2005
Figure 5.Sync Processing
The TVP7000supports RGB/YCbCr 4:4:4and YCbCr 4:2:2modes.Output timing is shown in Figure 6.All timing diagrams are shown for operation with internal PLL clock at phase 0.For a 4:2:2mode,CbCr data outputs at BOUT[9:0]pins.
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RGBin
HSYNC
DATACLK
RGBout
HSOUT RGBin
HSYNC
DATACLK
HSOUT GOUT
BOUT
4:4:4: RGB/YCbCr Output Timing
4:2:2 YCbCr Output Timing
TVP7000
SLES143–SEPTEMBER 2005
Figure 6.Output Timing Diagram
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I2C Host Interface
Reset and I2C Bus Address Selection I2C Operation
Power-up,Reset,and Initialization
TVP7000 SLES143–SEPTEMBER2005
Communication with the TVP7000device is via an I2C host interface.The I2C standard consists of two signals, serial input/output data(SDA)line and input clock line(SCL),which carry information between the devices connected to the bus.A third signal(I2CA)is used for slave address selection.Although an I2C system can be multi-mastered,the TVP7000can function as a slave device only.
Since SDA and SCL are kept open-drain at logic high output level or when the bus is not driven,the user should connect SDA and SCL to a positive supply voltage via a pull up resistor on the board.SDA is implemented bi-directional.The slave addresses select,terminal73(I2CA),enables the use of two TVP7000devices tied to the same I2C bus since it controls the least significant bit of the I2C device address
Table2.I2C Host Interface Terminal Description
SIGNAL TYPE DESCRIPTION
I2C A I Slave address selection
SCL I Input clock line
SDA I/O Input/output data line
TVP7000can respond to two possible chip addresses.The address selection is made at reset by an externally supplied level on the I2C A pin.The TVP7000device samples the level of terminal73at power-up or at the trailing edge of RESETB and configures the I2C bus address bit A0.The I2C A terminal has an internal pull-down resistor to pull the terminal low to set a zero.
Table3.I2C Host Interface Device Addresses
A6A5A4A3A2A1A0(I2C A)R/W HEX 1011100(default)1/0B9/B8 1011101(1)1/0BB/BA (1)If terminal73strapped to DVDD via a2.2k?resistor,I2C device address A0is set to1.
Data transfers occur utilizing the following illustrated formats.
S1*******ACK subaddress ACK send data ACK P
Read from I2C control registers
S1*******ACK subaddress ACK S1*******ACK receive data NAK P
S=I2C Bus Start condition
P=I2C Bus Stop condition
ACK=Acknowledge generated by the slave
NAK=Acknowledge generated by the master,for multiple byte read master with ACK each byte except last byte Subaddress=Subaddress byte
Data=Data byte,if more than one byte of DATA is transmitted(read and write),the subaddress pointer is automatically incremented
I2C bus address=Example shown that I2C A is in default mode.Write(B8h),Read(B9h)
No specific power-up sequence is required,but all power supplies should be active and stable within500ms of each other.Reset may be low during power-up,but must remain low for at least1μs after the power supplies become stable.Alternately reset may be asserted any time with minimum5ms delay after power-up and must remain asserted for at least1μs.Reset timing is shown in Figure7.It is also recommended that any I2C operation starts1μs after reset ended.Table4describes of the TVP7000terminals during and immediately after reset.
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Power
Reset
I2C
Control Registers
TVP7000
SLES143–SEPTEMBER2005
Table4.Reset Sequence
SIGNAL NAME DURING RESET RESET COMPLETED
ROUT[9:0],BOUT[9:0],BOUT[9:0]High impedence Output
HSOUT,VSOUT,SOGOUT High impedence Output
DATACLK High impedence Output
Figure7.Reset Timing
The TVP7000is initialized and controlled by a set of internal registers that define the operating parameters of the entire https://www.doczj.com/doc/6912804693.html,munication between the external controller and the TVP7000is through a standard I2C host port interface,as described earlier.
Table5shows the summary of these registers.Detailed programming information for each register is described sections.
Table5.Control Registers Summary(1)(2)
Register Name I2C Subaddress Default R/W
Chip Revision00h R
PLL Divide MSB01h69h R/W
PLL Divide LSB02h D0h R/W
PLL Control03h48h R/W Phase Select04h80h R/W Clamp Start05h80h R/W Clamp Width06h80h R/W HSYNC Output Width07h20h R/W
Blue Fine Gain08h80h R/W Green Fine Gain09h80h R/W
Red Fine Gain0Ah80h R/W
Blue Fine Offset0Bh80h R/W Green Fine Offset0Ch80h R/W
Red Fine Offset0Dh80h R/W
Sync Control10Eh40h R/W
PLL and Clamp Control0Fh4Eh R/W
(1)Register addresses not shown in the register map summary are reserved and must not be written to.
(2)Writing to or reading from any value labeled“Reserved”register may cause erroneous operation of the TVP7000.For registers with
reserved bits,a0b must be written to reserved bit locations unless otherwise stated.
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TVP7000
SLES143–SEPTEMBER2005 Table5.Control Registers Summary(continued)
Register Name I2C Subaddress Default R/W
Sync On Green Threshold10h B8h R/W
Sync Separator Threshold11h20h R/W
Pre-Coast12h00h R/W
Post-Coast13h00h R/W
Sync Detect Status14h R
Output Formatter15h00h R/W
Test Register16h00h R/W Reserved17h–18h
Input Mux Select119h00h R/W
Input Mux Select21Ah00h R/W
Blue and Green Coarse Gain1Bh55h R/W
Red Coarse Gain1Ch05h R/W
Fine Offset LSB1Dh00h R/W
Blue Coarse Offset1Eh20h R/W Green Coarse Offset1Fh20h R/W
Red Coarse Offset20h20h R/W HSOUT Output Start21h09h R/W
MISC Control22h00h R/W Reserved23h–25h
Automatic Level Control Enable26h00h R/W Reserved27h
Automatic Level Control Filter28h00h R/W Reserved29h
Fine Clamp Control2Ah00h R/W Power Control2Bh
ADC Setup2Ch00h R/W Coarse Clamp Control12Dh00h R/W
SOG Clamp2Eh00h R/W Reserved2Fh–30h
ALC Placement31h00h R/W
R=Read only
W=Write only
R/W=Read Write
Chip Revision
Subaddress00h Read Only
76543210
Chip revision[7:0]
Chip revision[7:0]:Chip revision number
17
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TVP7000
SLES143–SEPTEMBER 2005
PLL Divide
Subaddress
01h–02h
Default (69D0h)
7
6
5
4
3
2
10
PLL divide MSB [11:4]
PLL divide LSB [3:0]
Reserved
PLL divide [11:0]:PLL divide number sets the number of pixels per line.Controls the PLL feedback divider.MSB [11:4]bits should be loaded first whenever a change is required
PLL Control
Subaddress
03h
Default (48h)
7
6
5
4
3
210VCO[1:0]
Charge Pump Current [3:1]
Reserved
Reserved
Reserved
VCO [1:0]:Selects VCO frequency range
00=Ultra low 01=Low (default)10=Medium 11=High
Charge Pump Current [3:0]:Selects charge current of PLL LPF
000=Small (default)111=Large
Phase Select
Subaddress
04h
Default (80h)
7
6
5
4
3
2
1
0Phase Select [4:0]
Reserved
DIV2
Phase Select [4:0]:ADC Sampling clock phase select.(1LSB =360/32=11.25°)DATACLK Divide-by-2
0=DATACLK/11=DATACLK/2
Clamp Start
Subaddress
05h
Default (80h)
7
6
5
4
3
2
1
Clamp Start [7:0]
Clamp Start [7:0]:Positions the clamp signal an integer number of clock periods after the HSYNC signal.If external clamping is selected this value has no meaning
Clamp Width
Subaddress
06h
Default (80h)
7
6
5
4
3
2
1
Clamp Width [7:0]
Clamp Width [7:0]:Sets the width in pixels for clamp.See register Clamp Start.
18
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TVP7000
SLES143–SEPTEMBER2005 Table6.Recommended Fine Clamp Settings
VIDEO STANDARD CLAMP START CLAMP WIDTH
HDTV(tri-level)50(32h)32(20h)
SDTV(bi-level)6(06h)16(10h)
PC Graphics6(06h)16(10h)
HSYNC Output Width
Subaddress07h Default(20h)
76543210
HSOUT Width[7:0]
HSOUT Width[7:0]:Sets the width in pixels for HSYNC output.
Blue Fine Gain
Subaddress08h Default(80h)
76543210
Blue Gain[7:0]
Blue Gain[7:0]:PGA digital gain(contrast)for Blue channel applied after the ADC.Gain=1+Blue Gain[7:0]/256
80h=Recommended setting for700mVp-p input and default Coarse Gain(default).
Green Fine Gain
Subaddress09h Default(80h)
76543210
Green Gain[7:0]
Green Gain[7:0]:PGA digital gain(contrast)for Green channel applied after the ADC.Gain=1+Green Gain[7:0]/256
80h=Recommended setting for700mVp-p input and default Coarse Gain(default).
Red Fine Gain
Subaddress0Ah Default(80h) 76543210
Red Gain[7:0]
Red Gain[7:0]:Sets PGA digital gain(contrast)for Red channel applied after the ADC.Gain=1+Red Gain[7:0]/256
80h=Recommended setting for700mVp-p input and default Coarse Gain(default).
19
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TVP7000
SLES143–SEPTEMBER 2005
Blue Fine Offset
Subaddress
0Bh
Default (80h)
7
6
5
4
3
2
1
Blue Offset [9:2]
Blue Offset [9:2]:DC digital offset (brightness)for Blue channel applied after the ADC.
The default setting of 80h will place the bottom-level (YRGB)clamped output blank levels at 0and mid-level clamped (PbPr)output blank levels at 512.
Blue Offset Description 11111111maximum 1000000011LSB 100000000(default)01111111–1LSB 00000000
minimum
Green Fine Offset
Subaddress
0Ch
Default (80h)
7
6
5
4
3
2
1
Green Offset [9:2]
Green Offset [9:2]:DC digital offset (brightness)for Green channel applied after the ADC.See Red Fine Offset register at I 2C address 0x0B
Red Fine Offset
Subaddress
0Dh
Default (80h)
7
6
5
4
3
2
1
Red Offset [9:2]
Red Offset [9:2]:DC digital offset (brightness)for Red channel applied after the ADC.See Blue Fine Offset register at I 2C address 0x0B.
20